What's the difference between E4 & CG stepping and CG stepping?  Also, what's the diff. btwn. 130nmSOI & 90nmS
595977
until now i didn't find out the meaning of stepping. but i can tell you for sure that the 90nm structure (technology) is the newer one. 130nm is the older technology.\nnm = nano meters (10^-9 meters), this is the structure width (thickness) of the conductors inside the chip.\n\nbtw, Intels latest processors already use a 65nm structure.
448836
P4's are always faster than Celerons, even if they are stuck with a 133 (what Intel calls a 533, which it isn't) FSB.  I would recommend you buy the fastest socket 478 P4 that has a 133 FSB, which is quite a fast processor, actually: http://www.starmicro.net/detail.aspx?ID=121 \nIt's not a cheap one, but it's fast, overclockable, and is the only 133 FSB P4 with HyperThreading.  Here's the entire Socket 478 page at that same site: http://www.starmicro.net/SearchResult.aspx?CategoryID=28&WebID=c8f49aa1-ed21-471c-9699-530e75f98fa6 They are reputable, and have pretty good prices, along with ALOT of P4's & Celerons.
129691
See my answer to your next question.  For phase lead, C is in series and R in shunt.
1045311
pentium 4 is way faster. pentium 3 can be in the 800 MHz speed range, but pentium 4 can start near 1.4 GHz and work its way up to 3 GHz
758620
Assuming that you mean mov ax, 0 as the second part, yes it is really still faster on a tick by tick basis.  No, it probably doesn't matter as much at 2 GHz as it once did at 12 MHz or less.  There is only one other valid point to make here I think.  That is the instruction xor ax, ax will always absolutely cancel all of ax register's contents even if it is a subset of a larger eax register.  That is what I was told and lead to believe in all the materials I've studied and worked with.  Investigate this yourself for each prcoessor that you work with, but as far as I know, no processor will ever fail to zero a register in this manner where the statement xor ax, ax is valid.  I hope this helps.
269745
Good day:\n\nCircular buffer is very important to store analog data before transfering to digital format. Circular buffer is effective to swicth to many devices simultaneously. Intel webiste provide lots of DSP information!\n\nThank you, bye!
342505
I don't follow... AND gate means that ALL inputs must be HI to get a HI.  NAND inverts that, so...\n\nA (1)\nB (0).....0\nD (1)\n\nplus      ................... 1\n\nA (1)\nB (0).....0\nC (1)
521856
Constant current source, diode junction for temperature sensing, and a gain/offset circuit for scaling to 10mV/deg C.\n\nIf you look at the diagram in the product folder, its pretty easy to see whats going on.\nhttp://www.national.com/pf/LM/LM35.html\n\nThey get the accuracy without taking 2 measurements at different current levels, as is commonly done in diode temperature sensors, by wafer trimming.... which is why the LM35 costs so much more, than a simple diode sensor. The current source, and gain/offset circuitry uses minimal real estate on the die, with interconnects and physicial handling issues consuming almost as much as the circuit needs. The cost is a funtion of the extra time needed for trimming, and of course the manufacturing yield.
249130
GenuineIntel x86 Family 6 Model 8 Stepping 10 \n996MHz
822454
1.  = 1cm\n2.  = 2cm\n3.  = 4cm\n4.  = 7cm\n5.  = 11cm\n6.  = 16cm\n7.  = 22cm\n8.  = 29cm\n\ntotal length = 92cm\neach step adds more to the next length.  \nbetween the first and second step, add 1\nbetween the second and third step, add 2\nbetween the third and fourth step, add 3\nbetween the fourth and fifth step, add 4....\n\nand so on.
950705
In minicomputer O/S the no of procceses in one second is far much lower than that of a main frame. mainframes can operate in terms of tera bytes while minicomputers operate in terms of up to gigabits.\n\nits like comparing win vista and win 3.0 you can't run win 3.0 on a pentium 4 3.1 ghz it will be degrading your pc!
352289
The official language standard was updated a few years ago\nby both ANSI and ISO, to what is referred to as the "C99" standard.\nTo even be close to current, you'll want to be aware of the\nchanges made there.  You should be able to buy an electronic\ncopy from http://webstore.ansi.org or a hardcopy book from\nthe normal places (like amazon.com).\n\nConsiderably more current, however, will be what you find at\nthe ISO working group home page:\n\n    http://www.open-std.org/jtc1/sc22/wg14/\n\nHere you'll find the text of the existing defect reports,\ntechnical corrigendums, proposals for changes, as well as\nthe text of the rationale (which explains *why* certain\nstandards decisions were made).\n\nOne other source for both proposals for future changes as well\nas explanation of historical issues is:\n\n    http://www.lysator.liu.se/c/
26067
We are talking about levels of cache here.  The previous post is talking about the amount of level 1 cache as compared to what the original poster is talking about which is level 2 cache.  Am I wrong?\n\n\nBottom line, the pentium is faster.  This is due to the pentium's amount of cache that is "closer" to the processor.
194032
world's first microprocessor, the 4004, where the '4's were used to indicate that the device had a 4-bit data path. The 4004 was part of a four-chip system which also consisted of a 256-byte ROM, a 32-bit RAM, and a 10-bit shift register. The 4004 itself contained approximately 2,300 transistors and could execute 60,000 operations per second. The advantage (as far as Hoff was concerned) was that by simply changing the external program, the same device could be used for a multitude of future project
73999
I'm making two assumptions.  The total number of footsteps needed to go up the stairs is the number of steps + 1, the usual definition of number of steps.  And you want to know the "unit" rise and run, i.e., the r&r of each step.  If so,\nunit rise=total rise/(no. steps + 1)\nsame idea for unit run.\nIf you're actually making stairs, see the ref. for useful info like allowance for floor thickness, etc.
99892
Its a method to speed up your multiplication. Doesn't always speed up the operation.\n------\nTry googling it. \nU may also want to google - 'Booth Algorithm'
194528
A phase shift of pi/4 will cause a "one" to be interpreted as a "zero" or vice versa.  This corresponds to one quarter of a wavelength.  So by, lamda = c/f.  Then lamda/4 is the distance.  If the relative motion between tx and rx is approximately lamda/4 in one bit period, then the received bit will be in error.\n\nSee example 4.2 page 193 of the reference in "source(s)" for more details.