ARE source and drain interchangable in a MOSFET ?
606042
While the above answer is technically correct, it is not strictly correct.  Current does always flow from drain to source, but which terminal is the drain and which terminal is the source is entirely dependent on the voltage bias.  For instance, if you have it set up one way, with a Vgs allowing a current flow, if you switch that Vgs to be from gate to the other terminal, the current will flow the opposite way, and what used to be drain will now be considered source, and vice versa.  This is because the two terminals use the same doping, unlike BJTs.  This principle is used in analog mosfets.
41502
The plug may or not fit as they are usually differebt from mfg to mfg. If it does fit, make sure the voltage info is the same for both units before plugging it in as it may damage the unit.
980170
You aren't clear about whether the switch is on in both measurements.  If it is, then the voltage will be the same.  If not, then the voltage will be different because of the voltage drop across the internal resistance of the battery.
179798
RAM Random Access Memory\n\nROM Read Only Memory\n\nCMOS http://en.wikipedia.org/wiki/CMOS\n\nThe top two are self explanitory. One can be changed, one cant.
211231
It depends on both the type of current and the circuit.  For example, AC and DC currents passing through a circuit with reactive elements (capacitors and inductors) will much diffreently from one another.... Ohm's law always applies however...
486955
you will have an input on the ic itself.  when power is applied to either the input side-plus or negative side of the IC it will generate your output. An IC is the same as circuit put together in a smaller containment. Depending on the pin numbers of each IC each pin will determine what you must put into it the get what you want.
1111658
http://www.epanorama.net/circuits/vga2rgbs.html
201146
No, you can always use parts. Myself I use parts off old computers all the time. Just today I took the cmos battery out of an old computer for my laptop. Also If its not really old you can try and sell it instead of junking it.
1080382
Bi CMOS just refers to a process with both CMOS and bipolars (BJT's). First, CMOS is a process that takes a substrate (let's assume p-doping, which means equivalently that there is an excess of holes or lack of electrons). They then make a few implants to form a N-MOS device. They put down two n+ areas, called the source and drain spaced apart. They then add a gate oxide (the O in MOS) and add a metal on top.\nThis isn't exactly how they make it. Most processes now are self-aligned. What's done there is to put the gate oxide down everywhere first. Then, the oxide over source and drain areas are etched away. Next, the metal (usually postilion these days) is put over the oxide. Everything is bombarded with n+ ions, forming both the poly-silicon conductor and the source and drain areas.\nSimilar things happen for a PMOS device, except first the p- substrate is bombarded with a low density of n- ions (forming an n-well inside the substrate).\nHaving an n-mos and p-mos transistor in the same process is referred to as CMOS.\nTo form a bipolar transistor, one can re-use some of the CMOS process steps but add some others. The BJT is formed with a n- emitter, p- base, and n+ collector. In this case, the n-well (and a deep n-well) is used to from the n- emitter. Inside this, a second p-well is formed to make the p- base. On top of this, n+ ions are bombarded to form the n+ collector. This forms an n-p-n bipolar transistor.
335594
If you define a MOSFET as the Metal-Oxide-Semiconductor system which operates as how it does now, you cannot. Because it is limited by the fundamental physics.\n\nHowever, this doesn't prevent you from designing new transistors using other mechanism to achieve higher than 60mV/dec swing (which is still compatible with traditional CMOS process). Most of these transistors use impact ionization which can give < 60mV/dec.\n\nSimulation and device fabrication have demonstrated the concepts and published in major conferences such as IEDM.\n\nKodKodKod Learning Consulting -Here you get the answers!\nhttp://www.kodkodkod.com\nTo submit questions: http://www.kodkodkod.com/index_files/submitquestion.htm
831480
Voltage is dependent on the metals you use. The lemon however will have a lower output resistance. Because of this with the same load you may see more voltage the the lemon. But no load voltage will be the same.
389410
should we do your homework, make a drawing, send it to you?\nhere's a hint, tie 2 inputs of a nand gate together you get an inversion. MIKE
117060
EDO is obsolete. Even if there were some type of converter that would allow it to magically fit in a new motherboard, it would work painfully slow. Voltages and timing are completely wrong.\n\nEither sell it, or throw it away, IMO.
799002
in your cmos settings...according to type...at startup of course..
1064803
http://www.epanorama.net/circuits/parallel_output.html
930646
You probably want alpha, the common base current gain. In general, current gain is designated "beta," "alpha," or "gamma," for transistors connected in the common emitter, common base, or common collector configurations, respectively.  Beta = di(c)/di(b), the rate of change of collector current with respect to change in base current.  Alpha =di(c)/di(e), rate of change of collector current with respect to change in emitter current.  Gamma = di(e)/di(b), rate of change of emitter current with respect to change in base current.  Also, alpha = (beta)/(beta - 1), beta = (alpha)/(alpha - 1), and gamma = beta + 1.  For a detailed explanation, check out : http://www.tpub.com/neets/book7/25f.htm\n\nAnother possible answer: "amplification factor" for any amplifier circuit, regardless of configuration, or whether it uses tubes, BJTs, FETs, etc, refers to its voltage gain, dv(out)/dv(in), the change in output voltage with respect to a change in input voltage.
756063
A metal-oxide-semiconductor (MOS) structure is obtained by depositing a layer of silicon dioxide (SiO2) and a layer of metal (polycrystalline silicon is actually used instead of metal) on top of a semiconductor die. As the silicon dioxide is a dielectric material its structure is equivalent to a plane capacitor, with one of the electrodes replaced by a semiconductor.\n\nWhen a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a P-type semiconductor (with NA the density of holes), a positive VGB ( gate base voltage) tends to reduce the concentration of holes and increase the concentration of electrons. If VGB is high enough, the concentration of negative charge carriers near the gate is more than that of positive charges, in what is known as an inversion layer.\n\nThis structure with P-type body is the basis of the N-type MOSFET, which requires the addition of an N-type source and drain regions.\n\nPMOS (′pē′mös) :\n\n(electronics) Metal-oxide semiconductors that are made on n-type substrates, and whose active carriers are holes that migrate between p-type source and drain contacts. Derived from p-channel metal-oxide semiconductor. \n\nNMOS (′en′mös)\n \n(electronics) Metal-oxide semiconductors that are made on p-type substrates, and whose active carriers are electrons that migrate between n-type source and drain contacts. Derived from n-channel metal-oxide semiconductor. \n\n\n--------------------------------------------------------------------------------\nNMOS:\n\nnMOS logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. nMOS transistors have three modes of operation: cut-off, triode, and saturation (sometimes called active).\n\nThe n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.\n\nAs an example, here is a NOR gate in nMOS logic. If either input A or input B is high (logic 1, = True), the respective MOS transistor acts as a very low resistance between the output and the negative supply, forcing the output to be low (logic 0, = False). When both A and B are high, both transistors are conductive, creating an even lower resistance path to ground. The only case where the output is high is when both transistors are off, which occurs only when both A and B are low, thus satisfying the truth table of a NOR gate:\n\nA B A NOR B \n0 0 1 \n0 1 0 \n1 0 0 \n1 1 0 \n\nWhile nMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can be made with nMOSFETs), it has several shortcomings as well. The worst problem is that a DC current flows through an nMOS logic gate when the PDN is active, that is whenever the output is low. This leads to static power dissipation even when the circuit sits idle.\n\nAlso, nMOS circuits are slow to transition from low to high. When transitioning from high to low, the transistors provide low resistance, and the capacitative charge at the output drains away very quickly. But the resistance between the output and the positive supply rail is much greater, so the low to high transition takes longer. Using a resistor of lower value will speed up the process but also increases static power dissipation.\n\nAdditionally, the asymmetric input logic levels make nMOS circuits susceptible to noise.\n\nThese disadvantages are why nMOS logic was supplanted by CMOS logic both in low-power and in high-speed digital circuits, such as microprocessors, during the 1980s.\n\nPMos:\nFull details on:\nhttp://www.kettering.edu/~bguru/mosfets/PMOS-INT.pdf\n\nFor more info go to :\n\nht