Describe Register organisation and segmentation used in the 8086 microprocessor?
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http://en.wikipedia.org/wiki/8086\n\nAre you actually typing questions of your microprocessor assignment?
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6th generation?  Reference?\n\n6th Gen computers have 8 Floating Point CPU registers
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go to MS-dos and type "mem"\nu will be given all the details.
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well. it looks tiny to all of us, but infact it has millions of transistors arranged in particular circuitry within itself doing the job. \n\nthis link will help you in detail\nhttp://computer.howstuffworks.com/microprocessor.htm
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http://www.latrobe.edu.au/philosophy/phimvt/sympas/s15opprec.html\n\nhttp://en.wikipedia.org/wiki/Operator-precedence_parser\n\nhttp://compilers.iecc.com/comparch/article/98-03-108
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http://www.sdc.gc.ca/en/isp/cpp/cpptoc.shtml
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The AVR32 is a 32-bit RISC microprocessor architecture designed by Atmel. The microprocessor architecture was designed by a handful of people educated at the Norwegian University of Science and Technology, including lead designer Øyvind Strøm,PhD and CPU architect Erik Renno, M.Sc in Atmel's Norwegian design centre.\n\nThe AVR32 Architecture consists of several micro-architectures, most notably the AVR32A and AVR32B architectures, which describes fixed additions to the Instruction Set Architecture, configurations of the register file and the use of instruction and data-caches. Further descriptions are found in the AVR32 Architecture Manual.\n\nThe AVR32 Instruction Set Architecture consists of 16-bit (compact) and 32-bit (extended) instructions, with several specialized instructions not found in architectures like MIPS32 or ARMv5 or ARMv6 ISA. Several U.S. patents are filed for the AVR32 ISA and design platform.\n\nJust like the AVR 8-bit microcontroller architecture, the AVR32 was designed for extremely efficient code density and performance per clock cycle. Atmel used the independent benchmark consortium EEMBC to benchmark the architecture with various compilers and consistently outperformed both ARMv5 16-bit (THUMB) code and ARMv5 32-bit (ARM) code by as much as 50% on code-size and 3X on performance.\n\nThe AVR32 architecture is solely used in Atmel's own products and will appear in several devices in 2006. The first implementation of the AVR32 architecture is a 7-stage pipelined, cache-based design platform. This implementation of the AVR32 architecture adds SIMD (single instruction multiple data) DSP (digital signal processing) instructions to the RISC instruction-set, in addition to Java hardware acceleration.\n\nMost instructions are executed single-cycle and the MAC-unit is capable of performing 48 arithmetic in one cycle.\n\nAny resemblance to the 8-bit AVR is only with respect to the design center (both architectures originated out of Atmel Norway, Trondheim) and some of the debug-tools.
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First get a really good grip on how the hardware works, at least the basics.  Then learn X86 assembler and C languages and start in on the source code.  Comment everything that isn't already commented and ask about what you don't understand.  That's the hard way of course.  You could also start with some of the books and resources on the web.  Happy hunting!
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.MODEL small\ncr equ 0ah\nlf equ 0dh\nEOSTR equ '$'\n.stack 200h\n\n.data\ne db 'Enter the elements(0 to quit) :: '\n  db cr,lf,eostr\ns db 'The sorted elements are ::   '\n  db cr,lf,eostr\ntemp db 0\ncnt db 0\ntt db 0\nn  db 0\nnum db ?\n\n.code\ngetnum  proc near\n        ;push bx\n        mov temp,0\nscan:\n        mov ah,00h\n        int 16h\n        cmp al,13\n        jz  endscan\n\n        mov ah,0Eh\n        int 10h\n        sub al,30h\n\n        mov cl,al\n        mov al,temp\n        mov ah,0\n        mov bl,10\n        mul bl\n        add al,cl\n        mov temp,al\n        call scan\nendscan:\n        mov ah,0Eh\n        mov al,' '\n        int 10h\n        mov ah,0Eh\n        mov al,' '\n        int 10h\n        mov al,temp\n        ;pop bx\n        ret\ngetnum  endp\n\n\n\ndisp    proc near\n        ;push bx\n        mov bl,100\n        mov ch,1\nshow:\n        cmp bl,0\n        jz enddisp\n        cmp al,0\n        jnz n_zero\n        mov al,'0'\n        mov ah,0Eh\n        int 10h\n        mov al,0\n        jmp skip\nn_zero:\n        cmp ch,0\n        jz calc\n        cmp al,bl\n        jb  skip\ncalc:\n        mov ch,0\n        mov ah,0\n        div bl\n        mov cl,ah\n        add al,30h\n        mov ah,0Eh\n        int 10h\n        mov al,cl\n        jmp skip\nskip:\n        mov temp,al\n        mov al,bl\n        mov ah,0\n        mov bl,10\n        div bl\n        mov bl,al\n        mov al,temp\n        call show\n\nenddisp:\n        mov ah,0Eh\n        mov al,' '\n        int 10h\n        mov ah,0Eh\n        mov al,' '\n        int 10h\n        ;pop bx\n        ret\ndisp    endp\n\n\n\nstart:\n        mov ax,@data\n        mov ds,ax\n        mov dx,offset e\n        mov ah,9h\n        int 21h\n        mov bx,0\nread:\n        push bx\n        call getnum\n        pop bx\n        mov offset num[bx],al\n        inc bx\n        cmp al,0\n        jnz read\n\n        mov ah,0Eh\n        mov al,10\n        int 10h\n        mov ah,0Eh\n        mov al,13\n        int 10h\n\ncount:\n        mov al,offset num[bx]\n        cmp al,0\n        jz endcount\n        inc n\n        inc bx\n        call count\nendcount:\n\nbubble:\n        mov bx,0\nsort:\n        mov al,offset num[bx]\n        mov dl,al\n        mov cx,bx\n        inc bx\n        mov al,offset num[bx]\n        cmp al,0\n        jz endsort\n        cmp dl,al\n        jb n_exch\n        mov tt,al\n        mov al,dl\n        mov offset num[bx],al\n        mov al,tt\n        mov bx,cx\n        mov offset num[bx],al\nn_exch:\n        call sort\nendsort:\n        inc cnt\n        mov al,n\n        cmp al,cnt\n        jnz bubble\n\n        mov dx,offset s\n        mov ah,9h\n        int 21h\n        mov bx,0\nsho_arr:\n        mov al,offset num[bx]\n        cmp al,0\n        jz endpr\n        push bx\n        call disp\n        pop bx\n        inc bx\n        call sho_arr\nendpr:\n        mov ax,4c00h\n        int 21h\n\n        end start
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Program counter holds the address of either the first byte of the next instruction to be fetched for execution or the address of the next byte of a multi byte instruction, which has not been completely fetched. In both the cases it gets incremented automatically one by one as the instruction bytes get fetched. Also Program register keeps the address of the next instruction.
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Sounds like an all to common memory issue.\nTry Memtest86: http://www.memtest86.com/
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Learn assembler\n\nuse softice or linice to read memory changes\n\n\nsee what changes what and where then make a proggy to manipulate values in the memory.
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Segment registers hold the base address of where a particular segment begins in memory.  There is the code segment (CS), data segment (DS), stack segment (SS), and extra segment (ES).\n\nSegment registers are 16-bit registers which are ASSUMED to be holding a 20 bit number, because it is assumed you will add a zero to the end.  For example, if CS register is holding the hexadecimal value "13A6", then this value is actually representing the address "13A60".\n\nTo calculate a physical address, you take the address (called the logical address) and add it to the segment address.  For example, if you wanted to calculate the physical address which relates to logical address "1356" in the stack segment - you would also need to know what value is in the SS register, lets assume "2345":\n\nAdd the zero to the end of the segment address:\n23450\nThen add the two addresses together:\n23450 + 1356 = 247A6\n\n----------\n\nAdditional answer:\n\nThe processor uses 20 bit addresses.  The registers in the processor, however, are 16 bit registers (this is so older programs will still run on the system).  A 16 bit address allows you to access 65,535 memory cells.  A 20 bit address allows you to access 1,048,576 memory cells.  By design, the 16 bit registers will not allow all of the 1MB of memory to be accessed.  The answer to this is segment registers.  A segment register holds the address of where a 65K block of memory resides.  The segment register, although is a 16 bit register, is assumed to be holding a 20 bit address because you are supposed to add a zero to the end of whatever 16 bit number is in the segment register.\n\nFor example, if a segment register is holding the value\n"A45C"\nThis 16 bit number is actually representing the 20 bit value:\n"A45C0"\nbecause of adding the zero to the end.\n\nNow, if you have a 16 bit address, let's say "4B32" for example, you have to remember that this address is an offset (or logical) address residing inside a 65K block of memory.  Thus the physical address is calculated by finding out where the segment starts, then adding to it the offset address.  One of the segment registers will tell you where the segment begins.  Let's assume that the segment register is holding the value "A45C".  In this case, the segment begins at the 20 bit address "A45C0".  Add to that the offset address:  A45C0 + 4B32 = A90F2.  Therefore the address A90F2 is the 20 bit physical address that maps to the segment,offset address   A45C:4B32
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The SDK-86 (System Design Kit) was the first available computer using the Intel 8086 microprocessor. It was sold as a single board kit at a cheaper price than a single 8086 chip! because Intel thought that the success of a microprocessor depends on its evaluation by as many users as possible. All major components were socketed and the kit could be assembled by anyone having a limited technical knowledge thanks to a clear and complete assembly manual. The system could be used with the on-board keyboard and display or connected to a serial video terminal. \n\nThe internal ROM monitor offered the following commands:\n\nS (Substitute Memory): Displays / Modifies memory locations\nX (Examine / Modify registers) : Displays / Modifies 8086 registers\nD (Display memory): Displays memory content\nM (Move): Moves block of memory data\nI (Port Input): Receives data from input port\nO (Port Output): Send data to input port\nG (Go): Execute user program\nN (Single Step): Execute single program instruction\nR (Read File): Read object file from tape to memory\nW (Write File): Writes block of memory to tape. \n\n\nSDK - 86 Technical Information:\n\nNAME SDK-86\nMANUFACTURER Intel\nTYPE Home Computer\nORIGIN U.S.A.\nYEAR 1979\nBUILT IN LANGUAGE ROM Monitor\nKEYBOARD Hexadecimal 24 keys\nCPU Intel 8086\nSPEED 2.5 or 5 Mhz (jumper selectable)\nRAM 2 KB expandable to 4 KB\nROM 8 KB (Monitor)\nTEXT MODES 8-digit led\nI/O PORTS Processor bus, Parallel and Serial I/O\nPOWER SUPPLY + 5V, -12V external AC adaptor\nPRICE $780
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Hardware and software.
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Go here it has the info you need:\nhttp://en.wikipedia.org/wiki/Preprocessor
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I dont know if this will help but try these sites listed...\n\n\nhttp://gcc.gnu.org/\n\nhttp://www.goosee.com/x86/index.html