why logic gates is called so?
149057
Logic gates are referred to as such because they are "gates" (devices which stop or allow the flow of electricity) which operate according to the rules of Boolean logic.
1154893
Its what you just added in your additional comment....it doesnt have common sense, but we do. Well, some of us do anyway =) \n\nComputers are a man-made machine and it only does things that the human programs it to do, but in a more efficient and faster way. If we train it to do mathematical things, it will solve it for us faster. If we want it to store huge amount of data, it will do it for us.\n\nHowever, they do not have common sense. We cant teach it to think morally or ethically. It just does what we tell it to do. They will never experience human emotions or concepts...it will only provide us the foundation and software to allow us to enter them into its system, but they will not process it like humans do.\n\nIts limitations is how much data we put into it. How much memory it has. Its life expectancy is how long the hardware survives. They get replaced easily because as the years passes, the technology and components get better. \n\nTheir limitations is how we built them.
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the "software" is the languages such as verilog and vhdl\n\nthe code is firsts compiled \nthen the product is called a structural netlist.\nthen the netlist is run thru a synthesis program, ie synplicity, leonardo, percision synthsis, or design compiler.\nthis process converts the code into logic gates, with timing delays,\ncapacitances, and resistances.\nthen the netlist is send to floorplanning, for place and routing.\nthats the rough outline.
160354
- Its called Binary.\n- The binary consists of 0's and 1's\n- At basic level of hardware, whenever you pass a command to the computer, the operating system translates this to machine language.\n- The machine language interprets as 0's and 1's which means create some electronic signals.\n- Computer hardware is consists of thousands of Transsistors.\n- A '0' generation means the transistor produces the 'Negative' signal and '1' genaration means a 'positive' signal.\n- This how a computer's base system works and so the binary called 0 and 1.\n- Its a broad topic and so i can suggest you to search in Googe for more elaborated results.\n- all the best.\n--------------
131161
The transistor is an implementation of a Logic Gate.  It is a physical manifestation of a mathematical construct.  Put a charge here, and this other charge is allowed to flow.\n\nFirst we used mechanical relays to implement logic gates, which were clunky and prone to failure because they consisted of moving parts.  Then came the vacuum tube which also used electricity and had no moving parts, but were also space consuming and prone to oveheating.  The transistor was our next implementation of a Logic Gate, and were cheap, small, required little energy to operate, and required little maintenance because they are 'solid state'.\n\nI should note strictly speaking, the last time I was in the Boston Computer Museum, I saw a calculator built wholly from tinker toys and string.\n\nThe transistor became the fundamental building block of all logical implementations.  With the advent of the transistor, mathematical ideas could finally have the potential to be fully expressed as a practical reality.  Electricity then continued morphing from being a source of energy into a source of information.
322643
Its of or relating to the computer language, prolog, which is commonly used for AI programs.  Its a very flexible language.
416050
Well the answer is AND gate.\n\nthe output of an AND gate is 0 or low unless all its inputs are 1 or high.\n\ni.e for AND gate:\n\n0 and 0 gives 0\n0 and 1 gives 0\n1 ans 0 gives 0\n1 and 1 gives 1\n\ncheers
960782
refer to electronic devices and circuits by Milliman and Halkias\nElectronic principles by malvino
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Because it allows for one or the other but NOT both. This is the definition of exclusivity. An inclusive OR allows for one or the other or both.\n\nFor example, for an exclusive OR if one of the incoming values is 1, then the output of the gate would be 1. However the output would be 0 if both values are 1.
948953
It stands for the logical and operator. (As opposed to the binary and operator, which is written with a single &.)
527482
There are several types of flip flops (or flops as most designers call them). They all start with a basic building block: the SR (set reset) flip flop. To make one, you take two NAND gates (or two NOR gates), each with 2 inputs. One input on each gate becomes an input to the flip flop. The other input connects to the other gate's output. This is easier to draw than describe (look here: http://www.play-hookey.com/digital/rs_nand_latch.html).\n\nOf course, you'll want to add a clock, JK logic, D logic, T logic, but the basic core is always a cross-coupled inverting pair of gates.\n\nSo consider if both inputs are 1 and the inital output from each gate while it "starts up" happens to be 0 (doesn't matter, but just say it is). The top NAND gate sees {1,0} and  outputs a 1. So that means the bottom NAND gate sees {1,1} and outputs a 0. The outputs will always be inverted from each other (Q and Qnot).\n\nSo if we bring the bottom input low for a bit, the bottom NAND gate now sees {1,0} and outputs a 1. This means the top gate now sees {1,1} and outputs a 0. So if the bottom gate is our "Q" output, the bottom input is the set input (S). \n\nDo the same logic with the top input and you will see that it will "reset" the flop so that Q=0 and Qnot=1. Just don't bring both inputs low at once (that's what a JK flip flop is for).
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AND gate: if both the inputs are on then output is on.If even one of the inputs is off then output is off\n\nNOT gate: if input is on then output is off and vice versa.\n\nOR gate: If even one of the inputs is on then output is on.If both are off then output is off.If both inputs are on then output is on.
228827
The clocked D-latch solves several of the problems of storing output from a combinational circuit, but not all of them. Particularly, if D changes while C is true, the new value of D will appear at the output. Generally this is not what is wanted. If the stored value can change state more than once during a single clock pulse, the result is a hazard that might introduce a glitch later in the circuit. We must design the circuit so that the state can change only once per clock cycle. This can be accomplished by connecting two latches together as shown in Figure 6. The left half of the circuit is the clocked D-latch from the previous section. The right half of the circuit is a clocked S-R latch; however, the clock signal for the output section is the input clock signal inverted. The output of this device can only change once per clock cycle. The change occurs shortly after the falling edge of the clock cycle.
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A metal-oxide-semiconductor (MOS) structure is obtained by depositing a layer of silicon dioxide (SiO2) and a layer of metal (polycrystalline silicon is actually used instead of metal) on top of a semiconductor die. As the silicon dioxide is a dielectric material its structure is equivalent to a plane capacitor, with one of the electrodes replaced by a semiconductor.\n\nWhen a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a P-type semiconductor (with NA the density of holes), a positive VGB ( gate base voltage) tends to reduce the concentration of holes and increase the concentration of electrons. If VGB is high enough, the concentration of negative charge carriers near the gate is more than that of positive charges, in what is known as an inversion layer.\n\nThis structure with P-type body is the basis of the N-type MOSFET, which requires the addition of an N-type source and drain regions.\n\nPMOS (′pē′mös) :\n\n(electronics) Metal-oxide semiconductors that are made on n-type substrates, and whose active carriers are holes that migrate between p-type source and drain contacts. Derived from p-channel metal-oxide semiconductor. \n\nNMOS (′en′mös)\n \n(electronics) Metal-oxide semiconductors that are made on p-type substrates, and whose active carriers are electrons that migrate between n-type source and drain contacts. Derived from n-channel metal-oxide semiconductor. \n\n\n--------------------------------------------------------------------------------\nNMOS:\n\nnMOS logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. nMOS transistors have three modes of operation: cut-off, triode, and saturation (sometimes called active).\n\nThe n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.\n\nAs an example, here is a NOR gate in nMOS logic. If either input A or input B is high (logic 1, = True), the respective MOS transistor acts as a very low resistance between the output and the negative supply, forcing the output to be low (logic 0, = False). When both A and B are high, both transistors are conductive, creating an even lower resistance path to ground. The only case where the output is high is when both transistors are off, which occurs only when both A and B are low, thus satisfying the truth table of a NOR gate:\n\nA B A NOR B \n0 0 1 \n0 1 0 \n1 0 0 \n1 1 0 \n\nWhile nMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can be made with nMOSFETs), it has several shortcomings as well. The worst problem is that a DC current flows through an nMOS logic gate when the PDN is active, that is whenever the output is low. This leads to static power dissipation even when the circuit sits idle.\n\nAlso, nMOS circuits are slow to transition from low to high. When transitioning from high to low, the transistors provide low resistance, and the capacitative charge at the output drains away very quickly. But the resistance between the output and the positive supply rail is much greater, so the low to high transition takes longer. Using a resistor of lower value will speed up the process but also increases static power dissipation.\n\nAdditionally, the asymmetric input logic levels make nMOS circuits susceptible to noise.\n\nThese disadvantages are why nMOS logic was supplanted by CMOS logic both in low-power and in high-speed digital circuits, such as microprocessors, during the 1980s.\n\nPMos:\nFull details on:\nhttp://www.kettering.edu/~bguru/mosfets/PMOS-INT.pdf\n\nFor more info go to :\n\nht
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This depends on the logic family employed. For "standard CMOS" which is common today, +5V is 1 and 0V or ground is 0. However, other systems use other voltages. Lower voltages are common today for a few reasons. 3.3V logic, for example, is widely used where 3.3V is a 1 (and 0V is 0). However, it is possible to have negative logic. In addition, some high speed systems like ECL use voltages like -1.75V for a 0 and -0.9V for a 1 (this allows transistors to stay out of saturation which makes for fast switching but poor noise immunity and difficult design).
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Very-large-scale integration (VLSI) of systems of transistor-based circuits into integrated circuits on a single chip first occurred in the 1980s as part of the semiconductor and communication technologies that were being developed.\n\nThe first semiconductor chips held one transistor each. Subsequent advances added more and more transistors, and as a consequence more individual functions or systems were integrated over time. The microprocessor is a VLSI device.\n\nThe first "generation" of computers relied on vacuum tubes. Then came discrete semiconductor devices, followed by integrated circuits. The first Small-Scale Integration (SSI) ICs had small numbers of devices on a single chip – diodes, transistors, resistors and capacitors (no inductors though), making it possible to fabricate one or more logic gates on a single device. The fourth generation consisted of Large-Scale Integration (LSI), i.e. systems with at least a thousand logic gates. The natural successor to LSI was VLSI (many tens of thousands of gates on a single chip). Current technology has moved far past this mark and today's microprocessors have many millions of gates and hundreds of millions of individual transistors.\n\nAs of mid-2004, billion-transistor processors are not yet economically feasible for most uses, but they are achievable in laboratory settings, and they are clearly on the horizon as semiconductor fabrication moves from the current generation of 90 nanometer (90nm) processes to the next 65nm and 45nm generations.\n\nAt one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting more-than-VLSI levels of integration are no longer in widespread use. Even VLSI is now somewhat quaint, given the common assumption that all microprocessors are VLSI or better.
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The first electronic calculation device using binary logic was built by Konrad Zuse in 1938. Check out the first link below.\n\nCharles Babbage built or at least conceived the first mechanical difference engines that could sort punch cards and even be programmed by punchcards.