Return operand memory access translation.
483238
def _compute_memory_address(self, mem_operand):
        
        base = ReilRegisterOperand(mem_operand.base_reg.name, mem_operand.size)

        if mem_operand.displacement:
            address = self.temporal(mem_operand.size)

            if isinstance(mem_operand.displacement, ArmRegisterOperand):
                disp = ReilRegisterOperand(mem_operand.displacement.name, mem_operand.size)
            elif isinstance(mem_operand.displacement, ArmImmediateOperand):
                disp = ReilImmediateOperand(mem_operand.displacement.immediate, mem_operand.size)
            elif isinstance(mem_operand.displacement, ArmShiftedRegisterOperand):
                disp = self._compute_shifted_register(mem_operand.displacement)
            else:
                raise Exception("_compute_memory_address: displacement type unknown")

            if mem_operand.index_type == ARM_MEMORY_INDEX_PRE:
                if mem_operand.disp_minus:
                    self.add(self._builder.gen_sub(base, disp, address))
                else:
                    self.add(self._builder.gen_add(base, disp, address))
                self.add(self._builder.gen_str(address, base))
            elif mem_operand.index_type == ARM_MEMORY_INDEX_OFFSET:
                if mem_operand.disp_minus:
                    self.add(self._builder.gen_sub(base, disp, address))
                else:
                    self.add(self._builder.gen_add(base, disp, address))
            elif mem_operand.index_type == ARM_MEMORY_INDEX_POST:
                self.add(self._builder.gen_str(base, address))
                tmp = self.temporal(base.size)
                if mem_operand.disp_minus:
                    self.add(self._builder.gen_sub(base, disp, tmp))
                else:
                    self.add(self._builder.gen_add(base, disp, tmp))
                self.add(self._builder.gen_str(tmp, base))
            else:
                raise Exception("_compute_memory_address: indexing type unknown")

        else:
            address = base

        return address
748541
def instruction_LSL_memory(self, opcode, ea, m):
        
        r = self.LSL(m)
#        log.debug("$%x LSL memory value $%x << 1 = $%x and write it to $%x \t| %s" % (
#            self.program_counter,
#            m, r, ea,
#            self.cfg.mem_info.get_shortest(ea)
#        ))
        return ea, r & 0xff
598208
def get_operations(self,
                       indices: Sequence[LogicalIndex],
                       qubits: Sequence[ops.Qid]
                       ) -> ops.OP_TREE:
        """"""
512579
def translate(self):
        """"""
        varnames = set()
        ident = self.ident
        funcnames = set([ident])

        arg_exprs = []
        for arg in self.args:
            subexprs, subvars, subfuncs = arg.translate()
            varnames.update(subvars)
            funcnames.update(subfuncs)

            # Create a subexpression that joins the result components of
            # the arguments.
            arg_exprs.append(ex_call(
                ast.Attribute(ex_literal(u''), 'join', ast.Load()),
                [ex_call(
                    'map',
                    [
                        ex_rvalue(str.__name__),
                        ast.List(subexprs, ast.Load()),
                    ]
                )],
            ))

        subexpr_call = ex_call(
            FUNCTION_PREFIX + ident,
            arg_exprs
        )
        return [subexpr_call], varnames, funcnames
1190056
def get_memory_info(self) -> str:
        ''''''
        output, _ = self._execute(
            '-s', self.device_sn, 'shell', 'cat', '/proc/meminfo')
        return output
403414
def _retstr(ins):
    
    tmp, output = _str_oper(ins.quad[1], no_exaf=True)

    if not tmp:
        output.append('call __LOADSTR')
        REQUIRES.add('loadstr.asm')

    output.append('#pragma opt require hl')
    output.append('jp %s' % str(ins.quad[2]))
    return output
784518
def memoize_by_args(func):
    """"""
    memory = {}

    @functools.wraps(func)
    def memoized(*args):
        if args not in memory.keys():
            value = func(*args)
            memory[args] = value

        return memory[args]

    return memoized
1109001
def _translate_dst_oprnd(self, operand):
        
        if isinstance(operand, ReilRegisterOperand):
            return self._translate_dst_register_oprnd(operand)
        else:
            raise Exception("Invalid operand type")
1127871
def get_access_bits(self, c1, c2, c3):
        
        byte_6 = ((~c2[3] & 1) << 7) + ((~c2[2] & 1) << 6) + ((~c2[1] & 1) << 5) + ((~c2[0] & 1) << 4) + \
                 ((~c1[3] & 1) << 3) + ((~c1[2] & 1) << 2) + ((~c1[1] & 1) << 1) + (~c1[0] & 1)
        byte_7 = ((c1[3] & 1) << 7) + ((c1[2] & 1) << 6) + ((c1[1] & 1) << 5) + ((c1[0] & 1) << 4) + \
                 ((~c3[3] & 1) << 3) + ((~c3[2] & 1) << 2) + ((~c3[1] & 1) << 1) + (~c3[0] & 1)
        byte_8 = ((c3[3] & 1) << 7) + ((c3[2] & 1) << 6) + ((c3[1] & 1) << 5) + ((c3[0] & 1) << 4) + \
                 ((c2[3] & 1) << 3) + ((c2[2] & 1) << 2) + ((c2[1] & 1) << 1) + (c2[0] & 1)
        return byte_6, byte_7, byte_8
1347297
private Context translateArrayAssign(WyilFile.Expr.ArrayAccess lval, Expr rval, Context context) {
		// Translate src and index expressions
		Pair<Expr, Context> p1 = translateExpressionWithChecks(lval.getFirstOperand(), null, context);
		Pair<Expr, Context> p2 = translateExpressionWithChecks(lval.getSecondOperand(), null, p1.second());
		Expr source = p1.first();
		Expr index = p2.first();
		// Emit verification conditions to check access in bounds
		checkExpressionPreconditions(lval, p2.second());
		// Construct array update for "pass thru"
		Expr.Operator update = new Expr.ArrayUpdate(source, index, rval);
		return translateSingleAssignment((LVal) lval.getFirstOperand(), update, p2.second());
	}
542779
def to_raw_address(addr, section):
        """"""
        return addr - section.header.VirtualAddress + section.header.PointerToRawData
165525
def get_operand_expr(self, operand, mode="post"):
        
        if isinstance(operand, ReilRegisterOperand):
            if operand.name in self._arch_info.registers_all:
                # Process architectural registers (eax, ebx, etc.)
                expr = self.get_register_expr(operand.name, mode=mode)
            else:
                # Process temporal registers (t0, t1, etc.)
                var_name = self._get_var_name(operand.name, mode)
                expr = self._translator.make_bitvec(operand.size, var_name)
        elif isinstance(operand, ReilImmediateOperand):
            expr = smtsymbol.Constant(operand.size, operand.immediate)
        else:
            raise Exception("Invalid operand: %s" % str(operand))

        return expr
773458
def __taint_store(self, instr):
        
        # Get memory address.
        op2_val = self.__emu.read_operand(instr.operands[2])

        # Get taint information.
        op0_size = instr.operands[0].size
        op0_taint = self.get_operand_taint(instr.operands[0])

        # Propagate taint.
        self.set_memory_taint(op2_val, op0_size // 8, op0_taint)
400890
def meminfo():
    """"""
    f = open("/proc/meminfo")
    hwinfo = {}
    for line in f.readlines():
        meml = line.split()
        if (meml[0] == "MemTotal:"):
            mem = int(meml[1])
            hwinfo["Mem_MiB"] = mem/1024
        elif (meml[0] == "SwapTotal:"):
            swap = int(meml[1])
            hwinfo["Swap_MiB"] = swap/1024
    f.close()
    return hwinfo
1297388
def translate(self):
        """"""

        value = super().translate()
        if value is None or (isinstance(value, str) and value.strip() == ''):
            return None

        return int(value)
460286
def infer_operands_size(operands):
    
    size = None

    for oprnd in operands:
        if oprnd.size:
            size = oprnd.size
            break

    if size:
        for oprnd in operands:
            if not oprnd.size:
                oprnd.size = size
    else:
        for oprnd in operands:
            if isinstance(oprnd, X86ImmediateOperand) and not oprnd.size:
                oprnd.size = arch_info.architecture_size
436235
def in6_getnsma(a):
    

    r = in6_and(a, inet_pton(socket.AF_INET6, '::ff:ffff'))
    r = in6_or(inet_pton(socket.AF_INET6, 'ff02::1:ff00:0'), r)
    return r