CMN Ra, Rb

        Add the two registers and set the NZCV flags
        The result is discarded
        Ra and Rb must be low registers
497514
def CMN(self, params):
        
        Ra, Rb = self.get_two_parameters(self.TWO_PARAMETER_COMMA_SEPARATED, params)

        self.check_arguments(low_registers=(Ra, Rb))

        # CMN Ra, Rb
        def CMN_func():
            self.set_NZCV_flags(self.register[Ra], self.register[Rb],
                                self.register[Ra] + self.register[Rb], 'add')

        return CMN_func
156830
def small_register_machine(rom_size = 50, ram_size = 200, flash_size = 500):
	
	rom = memory.ROM(rom_size)
	ram = memory.RAM(ram_size)
	flash = device.Flash(flash_size)

	proc = processor.Processor()

	proc.register_memory_device(rom)
	proc.register_memory_device(ram)
	proc.register_device(flash)

	registers = [register.OutputRegister("out0", sys.stdout),
		register.Register("r0"),
		register.Register("r1"),
		register.Register("r2"),
		register.Register("r3"),
		register.Register("r4"),
		register.Register("r5"),
		register.Register("r6"),
		register.Register("r7"),
		register.Register("r8"),
		register.Register("r9"),
		register.Register("r10"),
		register.Register("r11"),
		register.Register("r12"),
		register.Register("r13"),
		register.Register("r14")]

	for r in registers:
		proc.add_register(r)

	for command in basic_commands:
		proc.register_command(command)

	return (proc, rom, ram, flash)
359542
public void setRegisters(InputRegister[] registers) {
        byteCount = registers.length * 2;
        setDataLength(byteCount + 1);

        this.registers = Arrays.copyOf(registers, registers.length);
    }
57818
def write_multiple_registers(addr, vals)
      s_val = ""
      vals.each do |reg|
        s_val << reg.to_word
      end

      query("\x10" + addr.to_word + vals.size.to_word + (vals.size * 2).chr + s_val)
      self
    end
224972
def write_multiple_registers(slave_id, starting_address, values):
    
    function = WriteMultipleRegisters()
    function.starting_address = starting_address
    function.values = values

    return _create_request_adu(slave_id, function.request_pdu)
227293
def PUSH(self, params):
        
        # TODO what registers are allowed to PUSH to? Low registers and LR
        # TODO PUSH should reverse the list, not POP
        RPushList = self.get_one_parameter(r'\s*{(.*)}(.*)', params).split(',')
        RPushList = [i.strip() for i in RPushList]
        # TODO should we make sure the register exists? probably not

        def PUSH_func():
            for register in RPushList:
                self.register['SP'] -= 4

                for i in range(4):
                    # TODO is this the same as with POP?
                    self.memory[self.register['SP'] + i] = ((self.register[register] >> (8 * i)) & 0xFF)

        return PUSH_func
1170052
def instruction_TFR(self, opcode, m):
        
        high, low = divmod(m, 16)
        dst_reg = self._get_register_obj(low)
        src_reg = self._get_register_obj(high)
        src_value = convert_differend_width(src_reg, dst_reg)
        dst_reg.set(src_value)
354667
def instruction_LD8(self, opcode, m, register):
        
#        log.debug("$%x LD8 %s = $%x" % (
#            self.program_counter,
#            register.name, m,
#        ))
        register.set(m)
        self.clear_NZV()
        self.update_NZ_8(m)
1302997
def rule_low_registers(self, arg):
        """"""
        r_num = self.check_register(arg)
        if r_num > 7:
            raise iarm.exceptions.RuleError(
                "Register {} is not a low register".format(arg))
647072
def instruction_EXG(self, opcode, m):
        
        high, low = divmod(m, 0x10)
        reg1 = self._get_register_obj(high)
        reg2 = self._get_register_obj(low)

        new_reg1_value = convert_differend_width(reg2, reg1)
        new_reg2_value = convert_differend_width(reg1, reg2)

        reg1.set(new_reg1_value)
        reg2.set(new_reg2_value)
963678
function rlist_lr(value) {
   var regs = value.split(",");
   var vals = { r0:1,r1:2,r2:4,r3:8,r4:16,r5:32,r6:64,r7:128,lr:256 };
   var bits = 0;
   for (var i in regs) {
     var reg = regs[i].trim();
     if (!(reg in vals))  throw "Unknown register name "+reg;
     bits |= vals[reg];
   }
   return bits;
  }
652008
def instruction_OR(self, opcode, m, register):
        
        a = register.value
        r = a | m
        register.set(r)
        self.clear_NZV()
        self.update_NZ_8(r)
301711
def SUBS(self, params):
        
        # This instruction allows for an optional destination register
        # If it is omitted, then it is assumed to be Rb
        # As defined in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0662b/index.html
        try:
            Ra, Rb, Rc = self.get_three_parameters(self.THREE_PARAMETER_COMMA_SEPARATED, params)
        except iarm.exceptions.ParsingError:
            Rb, Rc = self.get_two_parameters(self.TWO_PARAMETER_COMMA_SEPARATED, params)
            Ra = Rb

        if self.is_register(Rc):
            # SUBS Ra, Rb, Rc
            self.check_arguments(low_registers=(Ra, Rb, Rc))

            def SUBS_func():
                oper_1 = self.register[Rb]
                oper_2 = self.register[Rc]
                self.register[Ra] = self.register[Rb] - self.register[Rc]
                self.set_NZCV_flags(oper_1, oper_2, self.register[Ra], 'sub')
        else:
            if Ra == Rb:
                # SUBS Ra, Ra, #imm8
                self.check_arguments(low_registers=(Ra,), imm8=(Rc,))

                def SUBS_func():
                    oper_1 = self.register[Ra]
                    self.register[Ra] = self.register[Ra] - self.convert_to_integer(Rc[1:])
                    self.set_NZCV_flags(oper_1, self.convert_to_integer(Rc[1:]), self.register[Ra], 'sub')
            else:
                # SUBS Ra, Rb, #imm3
                self.check_arguments(low_registers=(Ra, Rb), imm3=(Rc,))

                def SUBS_func():
                    oper_1 = self.register[Rb]
                    self.register[Ra] = self.register[Rb] - self.convert_to_integer(Rc[1:])
                    self.set_NZCV_flags(oper_1, self.convert_to_integer(Rc[1:]), self.register[Ra], 'sub')

        return SUBS_func
1066181
void _emitRexR(int w, int opReg, int regCode) {
        if (is64()) {

            boolean r = (opReg & 0x8) != 0;
            boolean b = (regCode & 0x8) != 0;

            // w Default operand size(0=Default, 1=64 bits).
            // r Register field (1=high bit extension of the ModR/M REG field).
            // x Index field not used in RexR
            // b Base field (1=high bit extension of the ModR/M or SIB Base field).
            if (w != 0 || r || b || (_properties & (1 << PROPERTY_X86_FORCE_REX)) != 0) {
                _emitByte(0x40 | (w << 3) | (intValue(r) << 2) | intValue(b));
            }
        }
    }
1151206
def to_risc(compiler)
      l_reg = left.to_register(compiler, self)
      r_reg = right.to_register(compiler, self)
      compiler.add_code Risc.op( self , :- , l_reg , r_reg)
      compiler.add_code Risc::IsZero.new( self, false_jump.risc_label(compiler))
    end
261115
def STRB(self, params):
        
        Ra, Rb, Rc = self.get_three_parameters(self.THREE_PARAMETER_WITH_BRACKETS, params)

        if self.is_immediate(Rc):
            self.check_arguments(low_registers=(Ra, Rb), imm5=(Rc,))

            def STRB_func():
                self.memory[self.register[Rb] + self.convert_to_integer(Rc[1:])] = (self.register[Ra] & 0xFF)
        else:
            self.check_arguments(low_registers=(Ra, Rb, Rc))

            def STRB_func():
                self.memory[self.register[Rb] + self.register[Rc]] = (self.register[Ra] & 0xFF)

        return STRB_func
649832
def REV(self, params):
        
        Ra, Rb = self.get_two_parameters(self.TWO_PARAMETER_COMMA_SEPARATED, params)

        self.check_arguments(low_registers=(Ra, Rb))

        def REV_func():
            self.register[Ra] = ((self.register[Rb] & 0xFF000000) >> 24) | \
                                ((self.register[Rb] & 0x00FF0000) >> 8) | \
                                ((self.register[Rb] & 0x0000FF00) << 8) | \
                                ((self.register[Rb] & 0x000000FF) << 24)

        return REV_func