LDRH Ra, [Rb, Rc]
        LDRH Ra, [Rb, #imm6_2]

        Load a half word from memory into Ra
        Ra, Rb, and Rc must be low registers
483035
def LDRH(self, params):
        
        try:
            Ra, Rb, Rc = self.get_three_parameters(self.THREE_PARAMETER_WITH_BRACKETS, params)
        except iarm.exceptions.ParsingError:
            # LDRB Rn, [Rk] translates to an offset of zero
            Ra, Rb = self.get_two_parameters(r'\s*([^\s,]*),\s*\[([^\s,]*)\](,\s*[^\s,]*)*\s*', params)
            Rc = '#0'

        if self.is_immediate(Rc):
            self.check_arguments(low_registers=(Ra, Rb), imm6_2=(Rc,))

            def LDRH_func():
                # TODO does memory read up?
                if (self.register[Rb]) % 2 != 0:
                    raise iarm.exceptions.HardFault(
                        "Memory access not half word aligned; Register: {}  Immediate: {}".format(self.register[Rb],
                                                                                                  self.convert_to_integer(
                                                                                                      Rc[1:])))
                self.register[Ra] = 0
                for i in range(2):
                    self.register[Ra] |= (self.memory[self.register[Rb] + self.convert_to_integer(Rc[1:]) + i] << (8 * i))
        else:
            self.check_arguments(low_registers=(Ra, Rb, Rc))

            def LDRH_func():
                # TODO does memory read up?
                if (self.register[Rb] + self.register[Rc]) % 2 != 0:
                    raise iarm.exceptions.HardFault(
                        "Memory access not half word aligned; Register: {}  Immediate: {}".format(self.register[Rb],
                                                                                                  self.register[Rc]))
                self.register[Ra] = 0
                for i in range(2):
                    self.register[Ra] |= (self.memory[self.register[Rb] + self.register[Rc] + i] << (8 * i))

        return LDRH_func
290430
def UXTB(self, params):
        
        Ra, Rb = self.get_two_parameters(r'\s*([^\s,]*),\s*([^\s,]*)(,\s*[^\s,]*)*\s*', params)

        self.check_arguments(low_registers=(Ra, Rb))

        def UXTB_func():
            self.register[Ra] = (self.register[Rb] & 0xFF)

        return UXTB_func
807066
def STRH(self, params):
        
        Ra, Rb, Rc = self.get_three_parameters(self.THREE_PARAMETER_WITH_BRACKETS, params)

        if self.is_immediate(Rc):
            self.check_arguments(low_registers=(Ra, Rb), imm5=(Rc,))

            def STRH_func():
                for i in range(2):
                    self.memory[self.register[Rb] + self.convert_to_integer(Rc[1:]) + i] = ((self.register[Ra] >> (8 * i)) & 0xFF)
        else:
            self.check_arguments(low_registers=(Ra, Rb, Rc))

            def STRH_func():
                for i in range(2):
                    self.memory[self.register[Rb] + self.register[Rc] + i] = ((self.register[Ra] >> (8 * i)) & 0xFF)

        return STRH_func
301711
def SUBS(self, params):
        
        # This instruction allows for an optional destination register
        # If it is omitted, then it is assumed to be Rb
        # As defined in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0662b/index.html
        try:
            Ra, Rb, Rc = self.get_three_parameters(self.THREE_PARAMETER_COMMA_SEPARATED, params)
        except iarm.exceptions.ParsingError:
            Rb, Rc = self.get_two_parameters(self.TWO_PARAMETER_COMMA_SEPARATED, params)
            Ra = Rb

        if self.is_register(Rc):
            # SUBS Ra, Rb, Rc
            self.check_arguments(low_registers=(Ra, Rb, Rc))

            def SUBS_func():
                oper_1 = self.register[Rb]
                oper_2 = self.register[Rc]
                self.register[Ra] = self.register[Rb] - self.register[Rc]
                self.set_NZCV_flags(oper_1, oper_2, self.register[Ra], 'sub')
        else:
            if Ra == Rb:
                # SUBS Ra, Ra, #imm8
                self.check_arguments(low_registers=(Ra,), imm8=(Rc,))

                def SUBS_func():
                    oper_1 = self.register[Ra]
                    self.register[Ra] = self.register[Ra] - self.convert_to_integer(Rc[1:])
                    self.set_NZCV_flags(oper_1, self.convert_to_integer(Rc[1:]), self.register[Ra], 'sub')
            else:
                # SUBS Ra, Rb, #imm3
                self.check_arguments(low_registers=(Ra, Rb), imm3=(Rc,))

                def SUBS_func():
                    oper_1 = self.register[Rb]
                    self.register[Ra] = self.register[Rb] - self.convert_to_integer(Rc[1:])
                    self.set_NZCV_flags(oper_1, self.convert_to_integer(Rc[1:]), self.register[Ra], 'sub')

        return SUBS_func
750068
def SXTH(self, params):
        
        Ra, Rb = self.get_two_parameters(r'\s*([^\s,]*),\s*([^\s,]*)(,\s*[^\s,]*)*\s*', params)

        self.check_arguments(low_registers=(Ra, Rb))

        def SXTH_func():
            if self.register[Rb] & (1 << 15):
                self.register[Ra] = 0xFFFF0000 + (self.register[Rb] & 0xFFFF)
            else:
                self.register[Ra] = (self.register[Rb] & 0xFFFF)

        return SXTH_func
748541
def instruction_LSL_memory(self, opcode, ea, m):
        
        r = self.LSL(m)
#        log.debug("$%x LSL memory value $%x << 1 = $%x and write it to $%x \t| %s" % (
#            self.program_counter,
#            m, r, ea,
#            self.cfg.mem_info.get_shortest(ea)
#        ))
        return ea, r & 0xff
1089833
def STR(self, params):
        
        Ra, Rb, Rc = self.get_three_parameters(self.THREE_PARAMETER_WITH_BRACKETS, params)

        if self.is_immediate(Rc):
            if Rb == 'SP' or Rb == 'FP':
                self.check_arguments(low_registers=(Ra,), imm10_4=(Rc,))
            else:
                self.check_arguments(low_registers=(Ra, Rb), imm7_4=(Rc,))

            def STR_func():
                for i in range(4):
                    self.memory[self.register[Rb] + self.convert_to_integer(Rc[1:]) + i] = ((self.register[Ra] >> (8 * i)) & 0xFF)
        else:
            self.check_arguments(low_registers=(Ra, Rb, Rc))

            def STR_func():
                for i in range(4):
                    self.memory[self.register[Rb] + self.register[Rc] + i] = ((self.register[Ra] >> (8 * i)) & 0xFF)

        return STR_func
611123
def STM(self, params):
        
        # TODO what registers can be stored?
        Ra, RLoList = self.get_two_parameters(r'\s*([^\s,]*)!,\s*{(.*)}(.*)', params).split(',')
        RLoList = RLoList.split(',')
        RLoList = [i.strip() for i in RLoList]

        self.check_arguments(low_registers=[Ra] + RLoList)

        def STM_func():
            for i in range(len(RLoList)):
                for j in range(4):
                    self.memory[self.register[Ra] + 4*i + j] = ((self.register[RLoList[i]] >> (8 * j)) & 0xFF)
            self.register[Ra] += 4*len(RLoList)

        return STM_func
1209093
def instruction_ROR_memory(self, opcode, ea, m):
        
        r = self.ROR(m)
#        log.debug("$%x ROR memory value $%x >> 1 | Carry = $%x and write it to $%x \t| %s" % (
#            self.program_counter,
#            m, r, ea,
#            self.cfg.mem_info.get_shortest(ea)
#        ))
        return ea, r & 0xff
471144
def convert_ram_dp_ar(ADDR_WIDTH=8, DATA_WIDTH=8):
    '''  '''
    clka = Signal(bool(0))
    clkb = Signal(bool(0))
    wea = Signal(bool(0))
    web = Signal(bool(0))
    addra = Signal(intbv(0)[ADDR_WIDTH:])
    addrb = Signal(intbv(0)[ADDR_WIDTH:])
    dia = Signal(intbv(0)[DATA_WIDTH:])
    dib = Signal(intbv(0)[DATA_WIDTH:])
    doa = Signal(intbv(0)[DATA_WIDTH:])
    dob = Signal(intbv(0)[DATA_WIDTH:])
    toVerilog(ram_dp_ar, clka, clkb, wea, web, addra, addrb, dia, dib, doa, dob)
1269678
function(r, ptr, chr, len) {
        var i;
        for (i=0;i<len;i++) {
            r[ptr+i] = chr;
        }
    }
877426
def REV16(self, params):
        
        Ra, Rb = self.get_two_parameters(self.TWO_PARAMETER_COMMA_SEPARATED, params)

        self.check_arguments(low_registers=(Ra, Rb))

        def REV16_func():
            self.register[Ra] = ((self.register[Rb] & 0xFF00FF00) >> 8) | \
                                ((self.register[Rb] & 0x00FF00FF) << 8)

        return REV16_func
1082027
def TST(self, params):
        
        Ra, Rb = self.get_two_parameters(self.TWO_PARAMETER_COMMA_SEPARATED, params)

        self.check_arguments(low_registers=(Ra, Rb))

        def TST_func():
            result = self.register[Ra] & self.register[Rb]
            self.set_NZ_flags(result)

        return TST_func
1238958
def load_le32(buf, pos):
    """"""
    end = pos + 4
    if end > len(buf):
        raise BadRarFile('cannot load le32')
    return S_LONG.unpack_from(buf, pos)[0], pos + 4
224739
def _loadstr(ins):
    
    temporal, output = _str_oper(ins.quad[2], no_exaf=True)

    if not temporal:
        output.append('call __LOADSTR')
        REQUIRES.add('loadstr.asm')

    output.append('push hl')
    return output
744842
int /* udword_ppt */readBEdword(final short[] /* ubyte_ppt[4] */ptr,
			int pos) {
		return (((((short /* udword_ppt */) ptr[pos + 0]) << 24)
				+ (((short /* udword_ppt */) ptr[pos + 1]) << 16)
				+ (((short /* udword_ppt */) ptr[pos + 2]) << 8) + ((short /* udword_ppt */) ptr[pos + 3])) << 0);
	}
1349793
def _paload16(ins):
    ''' 
    '''
    output = _paddr(ins.quad[2])

    output.append('ld e, (hl)')
    output.append('inc hl')
    output.append('ld d, (hl)')
    output.append('ex de, hl')
    output.append('push hl')

    return output