Produce a MUL instruction.

    :param classical_reg: Left operand for the arithmetic operation. Also serves as the store target.
    :param right: Right operand for the arithmetic operation.
    :return: A ClassicalMul instance.
320441
def MUL(classical_reg, right):
    
    left, right = unpack_reg_val_pair(classical_reg, right)
    return ClassicalMul(left, right)
800536
def _ret8(ins):
    
    output = _8bit_oper(ins.quad[1])
    output.append('#pragma opt require a')
    output.append('jp %s' % str(ins.quad[2]))
    return output
943410
def raw_mul(self, e):
        
        e %= self._order
        P = self._infinity
        for bit in range(256):
            # add the power of the generator every time to make it more time-deterministic
            a = [P, P + self._powers[bit]]
            # choose the correct result
            P = a[e & 1]
            e >>= 1
        return P
1106003
def write_reg(self, addr, value, mask=0xFFFFFFFF, delay_us=0):
        
        return self.check_command("write target memory", self.ESP_WRITE_REG,
                                  struct.pack('<IIII', addr, value, mask, delay_us))
1039281
public Matrix4d mul(Matrix4dc right, Matrix4d dest) {
        if ((properties & PROPERTY_IDENTITY) != 0)
            return dest.set(right);
        else if ((right.properties() & PROPERTY_IDENTITY) != 0)
            return dest.set(this);
        else if ((properties & PROPERTY_TRANSLATION) != 0 && (right.properties() & PROPERTY_AFFINE) != 0)
            return mulTranslationAffine(right, dest);
        else if ((properties & PROPERTY_AFFINE) != 0 && (right.properties() & PROPERTY_AFFINE) != 0)
            return mulAffine(right, dest);
        else if ((properties & PROPERTY_PERSPECTIVE) != 0 && (right.properties() & PROPERTY_AFFINE) != 0)
            return mulPerspectiveAffine(right, dest);
        else if ((right.properties() & PROPERTY_AFFINE) != 0)
            return mulAffineR(right, dest);
        return mulGeneric(right, dest);
    }
283486
def apply_operator_overloading():
    
    # operator overloading is (unfortunately) not working for the following
    # cases:
    # int, float, str - should return appropriate type instead of a Publisher
    # len - should return an integer
    # "x in y" - is using __bool__ which is not working with Publisher
    for method in (
            '__lt__', '__le__', '__eq__', '__ne__', '__ge__', '__gt__',
            '__add__', '__and__', '__lshift__', '__mod__', '__mul__',
            '__pow__', '__rshift__', '__sub__', '__xor__', '__concat__',
            '__getitem__', '__floordiv__', '__truediv__'):
        def _op(operand_left, operand_right, operation=method):
            if isinstance(operand_right, Publisher):
                return CombineLatest(operand_left, operand_right,
                                     map_=getattr(operator, operation))
            return _MapConstant(operand_left, operand_right,
                                getattr(operator, operation))

        setattr(Publisher, method, _op)

    for method, _method in (
            ('__radd__', '__add__'), ('__rand__', '__and__'),
            ('__rlshift__', '__lshift__'), ('__rmod__', '__mod__'),
            ('__rmul__', '__mul__'), ('__rpow__', '__pow__'),
            ('__rrshift__', '__rshift__'), ('__rsub__', '__sub__'),
            ('__rxor__', '__xor__'), ('__rfloordiv__', '__floordiv__'),
            ('__rtruediv__', '__truediv__')):
        def _op(operand_left, operand_right, operation=_method):
            return _MapConstantReverse(operand_left, operand_right,
                                       getattr(operator, operation))

        setattr(Publisher, method, _op)

    for method, _method in (
            ('__neg__', operator.neg), ('__pos__', operator.pos),
            ('__abs__', operator.abs), ('__invert__', operator.invert),
            ('__round__', round), ('__trunc__', math.trunc),
            ('__floor__', math.floor), ('__ceil__', math.ceil)):
        def _op_unary(operand, operation=_method):
            return _MapUnary(operand, operation)

        setattr(Publisher, method, _op_unary)

    def _getattr(publisher, attribute_name):
        if not publisher.inherited_type or \
           not hasattr(publisher.inherited_type, attribute_name):
            raise AttributeError('Attribute %r not found' % attribute_name)
        return _GetAttr(publisher, attribute_name)

    setattr(Publisher, '__getattr__', _getattr)
431927
def _add_numeric_methods_binary(cls):
        
        cls.__add__ = _make_arithmetic_op(operator.add, cls)
        cls.__radd__ = _make_arithmetic_op(ops.radd, cls)
        cls.__sub__ = _make_arithmetic_op(operator.sub, cls)
        cls.__rsub__ = _make_arithmetic_op(ops.rsub, cls)
        cls.__rpow__ = _make_arithmetic_op(ops.rpow, cls)
        cls.__pow__ = _make_arithmetic_op(operator.pow, cls)

        cls.__truediv__ = _make_arithmetic_op(operator.truediv, cls)
        cls.__rtruediv__ = _make_arithmetic_op(ops.rtruediv, cls)

        # TODO: rmod? rdivmod?
        cls.__mod__ = _make_arithmetic_op(operator.mod, cls)
        cls.__floordiv__ = _make_arithmetic_op(operator.floordiv, cls)
        cls.__rfloordiv__ = _make_arithmetic_op(ops.rfloordiv, cls)
        cls.__divmod__ = _make_arithmetic_op(divmod, cls)
        cls.__mul__ = _make_arithmetic_op(operator.mul, cls)
        cls.__rmul__ = _make_arithmetic_op(ops.rmul, cls)
1170052
def instruction_TFR(self, opcode, m):
        
        high, low = divmod(m, 16)
        dst_reg = self._get_register_obj(low)
        src_reg = self._get_register_obj(high)
        src_value = convert_differend_width(src_reg, dst_reg)
        dst_reg.set(src_value)
441032
def mul(self, *args, **kwargs):
        
        return self._apply(operator.mul, *args, **kwargs)
241647
function(left, right) {
  if (!left && !right) {
    return { high: Long.fromNumber(0), low: Long.fromNumber(0) };
  }

  var leftHigh = left.shiftRightUnsigned(32);
  var leftLow = new Long(left.getLowBits(), 0);
  var rightHigh = right.shiftRightUnsigned(32);
  var rightLow = new Long(right.getLowBits(), 0);

  var productHigh = leftHigh.multiply(rightHigh);
  var productMid = leftHigh.multiply(rightLow);
  var productMid2 = leftLow.multiply(rightHigh);
  var productLow = leftLow.multiply(rightLow);

  productHigh = productHigh.add(productMid.shiftRightUnsigned(32));
  productMid = new Long(productMid.getLowBits(), 0)
    .add(productMid2)
    .add(productLow.shiftRightUnsigned(32));

  productHigh = productHigh.add(productMid.shiftRightUnsigned(32));
  productLow = productMid.shiftLeft(32).add(new Long(productLow.getLowBits(), 0));

  // Return the 128 bit result
  return { high: productHigh, low: productLow };
}
351393
def Multiplication(left: vertex_constructor_param_types, right: vertex_constructor_param_types, label: Optional[str]=None) -> Vertex:
    
    return Double(context.jvm_view().MultiplicationVertex, label, cast_to_double_vertex(left), cast_to_double_vertex(right))
1297482
def DIV(classical_reg, right):
    
    left, right = unpack_reg_val_pair(classical_reg, right)
    return ClassicalDiv(left, right)
900216
Expr mulDivMod() {
		Expr expr = nullSafe();
		for (Tok tok=peek(); tok.sym==Sym.MUL || tok.sym==Sym.DIV || tok.sym==Sym.MOD; tok=peek()) {
			move();
			expr = new Arith(tok.sym, expr, nullSafe(), location);
		}
		return expr;
	}
414171
def register(self, mimetype):
        """"""
        def dec(func):
            self._reg[mimetype] = func
            return func
        return dec
465761
def get_register_context(self):
        
        logging.debug("GDB getting register context")
        resp = b''
        reg_num_list = [reg.reg_num for reg in self._register_list]
        vals = self._context.read_core_registers_raw(reg_num_list)
        #print("Vals: %s" % vals)
        for reg, regValue in zip(self._register_list, vals):
            if reg.bitsize == 64:
                resp += six.b(conversion.u64_to_hex16le(regValue))
            else:
                resp += six.b(conversion.u32_to_hex8le(regValue))
            logging.debug("GDB reg: %s = 0x%X", reg.name, regValue)

        return resp
284805
def _classify_arithmetic(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
        
        matches = []

        # TODO: Review these restrictions.
        op_restrictions = {
            "+": lambda x, y: False,
            "-": lambda x, y: x == y,
            "|": lambda x, y: x == y,
            "&": lambda x, y: x == y,
            "^": lambda x, y: x == y,
        }

        # Check for "dst_reg <- src1_reg OP src2_reg" pattern.
        for op_name, op_fn in self._binary_ops.items():
            for src_1_reg, src_1_val in regs_init.items():
                # Make sure the *src* register was read.
                if src_1_reg not in read_regs:
                    continue

                for src_2_reg, src_2_val in regs_init.items():
                    # Make sure the *src* register was read.
                    if src_2_reg not in read_regs:
                        continue

                    for dst_reg, dst_val in regs_fini.items():
                        # Make sure the *dst* register was written.
                        if dst_reg not in written_regs:
                            continue

                        # Check restrictions.
                        if self._arch_regs_size[src_1_reg] != self._arch_regs_size[src_2_reg] or \
                            self._arch_regs_size[src_1_reg] != self._arch_regs_size[dst_reg]:
                            continue

                        # Avoid trivial operations.
                        if op_restrictions[op_name](src_1_reg, src_2_reg):
                            continue

                        size = self._arch_regs_size[src_1_reg]

                        if dst_val == op_fn(src_1_val, src_2_val) & (2**size - 1):
                            src = sorted([src_1_reg, src_2_reg])

                            src_ir = [
                                ReilRegisterOperand(src[0], self._arch_regs_size[src[0]]),
                                ReilRegisterOperand(src[1], self._arch_regs_size[src[1]])
                            ]

                            dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])

                            matches.append({
                                "src": src_ir,
                                "dst": [dst_reg_ir],
                                "op":  op_name
                            })

        return matches
645058
def op(self, i, o):
        
        for ii in range(len(o)):
            if is_register(o[ii]):
                o[ii] = o[ii].lower()

        if i == 'ld':
            self.set(o[0], o[1])
            return

        if i == 'push':
            if valnum(self.regs['sp']):
                self.set('sp', (self.getv(self.regs['sp']) - 2) % 0xFFFF)
            else:
                self.set('sp', None)
            self.stack.append(self.regs[o[0]])
            return

        if i == 'pop':
            self.set(o[0], self.stack and self.stack.pop() or None)
            if valnum(self.regs['sp']):
                self.set('sp', (self.getv(self.regs['sp']) + 2) % 0xFFFF)
            else:
                self.set('sp', None)
            return

        if i == 'inc':
            self.inc(o[0])
            return

        if i == 'dec':
            self.dec(o[0])
            return

        if i == 'rra':
            self.rr('a')
            return
        if i == 'rla':
            self.rl('a')
            return
        if i == 'rlca':
            self.rlc('a')
            return
        if i == 'rrca':
            self.rrc('a')
            return
        if i == 'rr':
            self.rr(o[0])
            return
        if i == 'rl':
            self.rl(o[0])
            return

        if i == 'exx':
            tmp = self.regs['bc']
            self.set('bc', "bc'")
            self.set("bc'", tmp)
            tmp = self.regs['de']
            self.set('de', "de'")
            self.set("de'", tmp)
            tmp = self.regs['hl']
            self.set('hl', "hl'")
            self.set("hl'", tmp)
            return

        if i == 'ex':
            tmp = self.get(o[1])
            self.set(o[1], o[0])
            self.set(o[0], tmp)
            return

        if i == 'xor':
            self.C = 0

            if o[0] == 'a':
                self.set('a', 0)
                self.Z = 1
                return

            if self.getv('a') is None or self.getv(o[0]) is None:
                self.Z = None
                self.set('a', None)
                return

            self.set('a', self.getv('a') ^ self.getv(o[0]))
            self.Z = int(self.get('a') == 0)
            return

        if i in ('or', 'and'):
            self.C = 0

            if self.getv('a') is None or self.getv(o[0]) is None:
                self.Z = None
                self.set('a', None)
                return

            if i == 'or':
                self.set('a', self.getv('a') | self.getv(o[0]))
            else:
                self.set('a', self.getv('a') & self.getv(o[0]))

            self.Z = int(self.get('a') == 0)
            return

        if i in ('adc', 'sbc'):
            if len(o) == 1:
                o = ['a', o[0]]

            if self.C is None:
                self.set(o[0], 'None')
                self.Z = None
                self.set(o[0], None)
                return

            if i == 'sbc' and o[0] == o[1]:
                self.Z = int(not self.C)
                self.set(o[0], -self.C)
                return

            if self.getv(o[0]) is None or self.getv(o[1]) is None:
                self.set_flag(None)
                self.set(o[0], None)
                return

            if i == 'adc':
                val = self.getv(o[0]) + self.getv(o[1]) + self.C
                if is_8bit_register(o[0]):
                    self.C = int(val > 0xFF)
                else:
                    self.C = int(val > 0xFFFF)
                self.set(o[0], val)
                return

            val = self.getv(o[0]) - self.getv(o[1]) - self.C
            self.C = int(val < 0)
            self.Z = int(val == 0)
            self.set(o[0], val)
            return

        if i in ('add', 'sub'):
            if len(o) == 1:
                o = ['a', o[0]]

            if i == 'sub' and o[0] == o[1]:
                self.Z = 1
                self.C = 0
                self.set(o[0], 0)
                return

            if not is_number(self.get(o[0])) or not is_number(self.get(o[1])) is None:
                self.set_flag(None)
                self.set(o[0], None)
                return

            if i == 'add':
                val = self.getv(o[0]) + self.getv(o[1])
                if is_8bit_register(o[0]):
                    self.C = int(val > 0xFF)
                    val &= 0xFF
                    self.Z = int(val == 0)
                    self.S = val >> 7
                else:
                    self.C = int(val > 0xFFFF)
                    val &= 0xFFFF

                self.set(o[0], val)
                return

            val = self.getv(o[0]) - self.getv(o[1])
            if is_8bit_register(o[0]):
                self.C = int(val < 0)
                val &= 0xFF
                self.Z = int(val == 0)
                self.S = val >> 7
            else:
                self.C = int(val < 0)
                val &= 0xFFFF

            self.set(o[0], val)
            return

        if i == 'neg':
            if self.getv('a') is None:
                self.set_flag(None)
                return

            val = -self.getv('a')
            self.set('a', val)
            self.Z = int(not val)
            val &= 0xFF
            self.S = val >> 7
            return

        if i == 'scf':
            self.C = 1
            return

        if i == 'ccf':
            if self.C is not None:
                self.C = int(not self.C)
            return

        if i == 'cpl':
            if self.getv('a') is None:
                return

            self.set('a', 0xFF ^ self.getv('a'))
            return

        # Unknown. Resets ALL
        self.reset()