Helper to extract mem bits and ports for estimation.
192581
def _bits_ports_and_isrom_from_memory(mem):
    
    is_rom = False
    bits = 2**mem.addrwidth * mem.bitwidth
    read_ports = len(mem.readport_nets)
    try:
        write_ports = len(mem.writeport_nets)
    except AttributeError:  # dealing with ROMs
        if not isinstance(mem, RomBlock):
            raise PyrtlInternalError('Mem with no writeport_nets attribute'
                                     ' but not a ROM? Thats an error')
        write_ports = 0
        is_rom = True
    ports = max(read_ports, write_ports)
    return bits, ports, is_rom
618468
def _gather_buffer_space():
    '''
    
    '''
    if HAS_PSUTIL and psutil.version_info >= (0, 6, 0):
        # Oh good, we have psutil. This will be quick.
        total_mem = psutil.virtual_memory().total
    else:
        # Avoid loading core grains unless absolutely required
        import platform
        import salt.grains.core
        # We need to load up ``mem_total`` grain. Let's mimic required OS data.
        os_data = {'kernel': platform.system()}
        grains = salt.grains.core._memdata(os_data)
        total_mem = grains['mem_total'] * 1024 * 1024
    # Return the higher number between 5% of the system memory and 10MiB
    return max([total_mem * 0.05, 10 << 20])
926605
def GetIcmpStatistics():
    """"""
    statistics = MIB_ICMP()
    _GetIcmpStatistics(byref(statistics))
    results = _struct_to_dict(statistics)
    del(statistics)
    return results
665805
def read_discrete_inputs(addr, ninputs)
      query("\x2" + addr.to_word + ninputs.to_word).unpack_bits[0..ninputs-1]
    end
1227743
def scan(self):
        """"""
        found = []
        for addr in range(0,0x80):
            try:
                self._i2c_bus.read_byte(addr)
            except OSError:
                continue
            found.append(addr)
        return found
720042
def extract_ms(self, x, y):
        
        ms = np.zeros(self.conf.ndims)
        ms[self.expl_dims] = x
        ms[self.inf_dims] = y
        return ms[self.conf.m_dims], ms[self.conf.s_dims]
342474
def get_data(self, size=None, addr=None):
        '''
        
        '''
        # readback memory offset
        if addr is None:
            addr = self._mem_bytes

        if size and self._mem_bytes < size:
            raise ValueError('Size is too big')

        if size is None:
            return self._intf.read(self._conf['base_addr'] + self._spi_mem_offset + addr, self._mem_bytes)
        else:
            return self._intf.read(self._conf['base_addr'] + self._spi_mem_offset + addr, size)
677600
def memsize(self):
        
        return self.size + 1 + TYPE.size(gl.BOUND_TYPE) * len(self.bounds)
87392
def _int_generator(descriptor, bitwidth, unsigned):
    ''
    vals = list(values.get_integers(bitwidth, unsigned))
    return gen.IterValueGenerator(descriptor.name, vals)
890330
function(res, pid) {
  var lines = res.split('\n')
    , data = s(lines[1]).collapseWhitespace().s
    , dataParts = data.split(' ');

  return {
    pid: pid
  , cpu: dataParts[0] || '0.0'
  , mem: dataParts[1] || '0'
  };
}
513140
def _memcopy(ins):
    
    output = _16bit_oper(ins.quad[3])
    output.append('ld b, h')
    output.append('ld c, l')
    output.extend(_16bit_oper(ins.quad[1], ins.quad[2], reversed=True))
    output.append('ldir')  # ***

    return output
941760
def result(i):
    
    ins = inst(i)
    op = oper(i)

    if ins in ('or', 'and') and op == ['a']:
        return ['f']

    if ins in {'xor', 'or', 'and', 'neg', 'cpl', 'daa', 'rld', 'rrd', 'rra', 'rla', 'rrca', 'rlca'}:
        return ['a', 'f']

    if ins in {'bit', 'cp', 'scf', 'ccf'}:
        return ['f']

    if ins in {'sub', 'add', 'sbc', 'adc'}:
        if len(op) == 1:
            return ['a', 'f']
        else:
            return single_registers(op[0]) + ['f']

    if ins == 'djnz':
        return ['b', 'f']

    if ins in {'ldir', 'ldi', 'lddr', 'ldd'}:
        return ['f', 'b', 'c', 'd', 'e', 'h', 'l']

    if ins in {'cpi', 'cpir', 'cpd', 'cpdr'}:
        return ['f', 'b', 'c', 'h', 'l']

    if ins in ('pop', 'ld'):
        return single_registers(op[0])

    if ins in {'inc', 'dec', 'sbc', 'rr', 'rl', 'rrc', 'rlc'}:
        return ['f'] + single_registers(op[0])

    if ins in ('set', 'res'):
        return single_registers(op[1])

    return []
1227819
def _extract_section(sect_req, elffile, mem=None):
        
        for nseg, section in enumerate(elffile.iter_sections()):
            request = sect_req.get(section.name, None)
            if request:
                request.set_found(True)
                request.set_sect_properties(section.header.sh_addr,
                                            section.header.sh_size)
                if mem:
                    mem.add_vma(section.header.sh_addr, section.data())
                else:
                    request.memory.add_vma(section.header.sh_addr, section.data())
1196285
def bfi(value, msb, lsb, field):
    """"""
    mask = bitmask((msb, lsb))
    value &= ~mask
    value |= (field << lsb) & mask
    return value
518043
def get_kernel_data(self):
        """"""
        return {
            'nmsimplex_scratch': LocalMemory(
                'mot_float_type', self._nmr_parameters * 2 + (self._nmr_parameters + 1) ** 2 + 1),
            'initial_simplex_scale': LocalMemory('mot_float_type', self._nmr_parameters)
        }
521656
def convert_ram_sp_ar(ADDR_WIDTH=8, DATA_WIDTH=8):
    '''  '''
    clk = Signal(bool(0))
    we = Signal(bool(0))
    addr = Signal(intbv(0)[ADDR_WIDTH:])
    di = Signal(intbv(0)[DATA_WIDTH:])
    do = Signal(intbv(0)[DATA_WIDTH:])
    toVerilog(ram_sp_ar, clk, we, addr, di, do)
400890
def meminfo():
    """"""
    f = open("/proc/meminfo")
    hwinfo = {}
    for line in f.readlines():
        meml = line.split()
        if (meml[0] == "MemTotal:"):
            mem = int(meml[1])
            hwinfo["Mem_MiB"] = mem/1024
        elif (meml[0] == "SwapTotal:"):
            swap = int(meml[1])
            hwinfo["Swap_MiB"] = swap/1024
    f.close()
    return hwinfo