export zoo_clt, zoo_clt_file

using LogicCircuits
using Pkg.Artifacts

#####################
# circuit loaders from module zoo
#####################

# TODO move this to a Lerche.jl parser and use Base.{read,parse}

zoo_clt_file(name) = 
    artifact"circuit_model_zoo" * LogicCircuits.zoo_version * "/clts/$name"
    
zoo_clt(name) = 
    parse_clt(zoo_clt_file(name))


using MetaGraphs: MetaDiGraph, set_prop!, props, add_edge!

"Parse a clt from given file"
function parse_clt(filename::String)::MetaDiGraph
    f = open(filename)
    n = parse(Int32,readline(f))
    n_root = parse(Int32,readline(f))
    clt = MetaDiGraph(n)
    for i in 1 : n_root
        root, prob = split(readline(f), " ")
        root, prob = parse(Int32, root), parse(Float64, prob)
        set_prop!(clt, root, :parent, 0)
        set_prop!(clt, root, :cpt, Dict(1=>prob,0=>1-prob))
    end

    for i = 1 : n - n_root
        dst, src, prob1, prob0 = split(readline(f), " ")
        dst, src, prob1, prob0 = parse(Int32, dst), parse(Int32, src), parse(Float64, prob1), parse(Float64, prob0)
        add_edge!(clt, src,dst)
        set_prop!(clt, dst, :parent, src)
        set_prop!(clt, dst, :cpt, Dict((1,1)=>prob1, (0,1)=>1-prob1, (1,0)=>prob0, (0,0)=>1-prob0))
    end
    return clt
end
