Submitted by KupiaSec, also found by Zubat
Incorrect dispute game resolution - it will make True root claim to be False.
MIPS-ISA: Page 153(A-141)
SRAV instruction does arithmetic shift right, the bit shift count is specified by the low-order five bits of rs register.
However, in implementation it does not validate low-level five bits of rs register, but use it as a whole for shift.
As a result, if any of bits after 5th bit is one, the shift results will always be zero.
As it did for other shifts, it should apply & 0x1F before shifting.
Context
mbaxter (Optimism) confirmed and commented:
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