As per the MIPS ISA, sc will write a 1 to rt if a write is atomic and a 0 to rt is non-atomic. A write is atomic if the value of the memory address pointed to by the sc instruction has not been changed since the value of the same memory address has been loaded by the ll instruction. However, the sc implementation in the MIPS code will always write a 1 regardless of whether the write is atomic or non-atomic. 
Since the VM is likely to not be implementing concurrency, the only impact of this is that it deviates from the MIPS specification, as the offchain MIPS VM has the same bug. 
