The mult, multu, div and divu instructions are only supposed to write to HI, LO special registers. However, since they are R-type instructions, they can still have a non-zero rd value, though this would be an invalid instruction and lead to undefined behaviour. The MIPS VM do not zero out the rd value if the rd value for the mult, multu, div, divu instructions.
Therefore, if the rd value is non-zero, the register referenced by rd which is passed into _storeReg variable will be overwritten by val which will be 0, as seen in the snippet below.
Since this is undefined behaviour, it does not contradict any MIPS spec and the onchain and offchain MIPS VM have the same behaviour but it might probably be best to resolve this.
