RORS [Ra,] Ra, Rc

        Rotate shift right Rb by Rc or imm5 and store the result in Ra
        The first two operands must be the same register
        Ra and Rc must be low registers
        The first register is optional
436111
def RORS(self, params):
        
        # This instruction allows for an optional destination register
        # If it is omitted, then it is assumed to be Rb
        # As defined in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0662b/index.html
        try:
            Ra, Rb, Rc = self.get_three_parameters(self.THREE_PARAMETER_COMMA_SEPARATED, params)
        except iarm.exceptions.ParsingError:
            Rb, Rc = self.get_two_parameters(self.TWO_PARAMETER_COMMA_SEPARATED, params)
            Ra = Rb

        # TODO implement this function
        # TODO figure out the last shifted bit
        # TODO figure out how to wrap bits around
        raise iarm.exceptions.NotImplementedError

        # RORS Ra, Ra, Rb
        self.check_arguments(low_registers=(Ra, Rc))
        self.match_first_two_parameters(Ra, Rb)

        def RORS_func():
            raise NotImplementedError

        return RORS_func
1360056
def to_risc(compiler)
      const_reg = @right.to_register(compiler , original_source)
      left_slots = @left.slots
      case @left.known_object
      when Symbol
        sym_to_risc(compiler , const_reg)
      when Parfait::CacheEntry
        left = compiler.use_reg( :CacheEntry )
        compiler.add_code Risc.load_constant(original_source, @left.known_object , left)
        compiler.add_code Risc.reg_to_slot(original_source, const_reg , left, left_slots.first)
      else
        raise "We have left #{@left.known_object}"
      end
      compiler.reset_regs
    end
745593
def _rlFindStart(rl,lz,pot,lower=False):
    """"""
    rtry= 2.*rl
    while (2.*lower-1.)*_rlfunc(rtry,lz,pot) > 0.:
        if lower:
            rtry/= 2.
        else:
            rtry*= 2.
    return rtry
492656
def _translate_src_register_oprnd(self, operand):
        
        reg_info = self._arch_alias_mapper.get(operand.name, None)

        if reg_info:
            var_base_name, offset = reg_info

            var_size = self._arch_regs_size[var_base_name]
        else:
            var_base_name = operand.name
            var_size = operand.size

        var_name = self._get_var_name(var_base_name)
        ret_val = self.make_bitvec(var_size, var_name)

        if reg_info:
            ret_val = smtfunction.extract(ret_val, offset, operand.size)

        return ret_val
1348952
function addArr(arr1, arr2, shift = 0) {
  arr2.forEach((singlet, i) => {
    addNum(arr1, singlet, i + shift);
  });
}
1231640
def SXTB(self, params):
        
        Ra, Rb = self.get_two_parameters(r'\s*([^\s,]*),\s*([^\s,]*)(,\s*[^\s,]*)*\s*', params)

        self.check_arguments(low_registers=(Ra, Rb))

        def SXTB_func():
            if self.register[Rb] & (1 << 7):
                self.register[Ra] = 0xFFFFFF00 + (self.register[Rb] & 0xFF)
            else:
                self.register[Ra] = (self.register[Rb] & 0xFF)

        return SXTB_func
769712
public static final Mem tword_ptr_abs(long target, Register index, int shift, long disp, SEGMENT segmentPrefix) {
        return _ptr_build_abs(target, index, shift, disp, segmentPrefix, SIZE_TWORD);
    }
1169036
def rotate(r, pos)
      return (0..2).map do |i|
        (0..2).inject(0) { |sum, j| sum + r[i][j] * pos[j] }
      end
    rescue => e
      raise
    end
1172845
def MOVS(self, params):
        
        Ra, Rb = self.get_two_parameters(self.TWO_PARAMETER_COMMA_SEPARATED, params)

        if self.is_immediate(Rb):
            self.check_arguments(low_registers=[Ra], imm8=[Rb])

            def MOVS_func():
                self.register[Ra] = self.convert_to_integer(Rb[1:])

                # Set N and Z status flags
                self.set_NZ_flags(self.register[Ra])

            return MOVS_func
        elif self.is_register(Rb):
            self.check_arguments(low_registers=(Ra, Rb))

            def MOVS_func():
                self.register[Ra] = self.register[Rb]

                self.set_NZ_flags(self.register[Ra])

            return MOVS_func
        else:
            raise iarm.exceptions.ParsingError("Unknown parameter: {}".format(Rb))
450212
def mix_r!(i, j, c = nil)
      @left.mix_r!(i, j, c)
      @body.mix_r!(i, j, c)
      self
    end
1327710
void _emitRexRM(int w, int opReg, Operand rm) {
        if (is64()) {

            boolean r = (opReg & 0x8) != 0;
            boolean x = false;
            boolean b = false;

            if (rm.isReg()) {
                b = (((BaseReg) rm).code() & 0x8) != 0;

            } else if (rm.isMem()) {
                x = (((Mem) rm).index() & 0x8) != 0 && ((Mem) rm).index() != NO_REG;
                b = (((Mem) rm).base() & 0x8) != 0 && ((Mem) rm).base() != NO_REG;
            }

            // w Default operand size(0=Default, 1=64 bits).
            // r Register field (1=high bit extension of the ModR/M REG field).
            // x Index field (1=high bit extension of the SIB Index field).
            // b Base field (1=high bit extension of the ModR/M or SIB Base field).
            if (w != 0 || r || x || b || (_properties & (1 << PROPERTY_X86_FORCE_REX)) != 0) {
                _emitByte(0x40 | (w << 3) | (intValue(r) << 2) | (intValue(x) << 1) | intValue(b));
            }
        }
    }
483035
def LDRH(self, params):
        
        try:
            Ra, Rb, Rc = self.get_three_parameters(self.THREE_PARAMETER_WITH_BRACKETS, params)
        except iarm.exceptions.ParsingError:
            # LDRB Rn, [Rk] translates to an offset of zero
            Ra, Rb = self.get_two_parameters(r'\s*([^\s,]*),\s*\[([^\s,]*)\](,\s*[^\s,]*)*\s*', params)
            Rc = '#0'

        if self.is_immediate(Rc):
            self.check_arguments(low_registers=(Ra, Rb), imm6_2=(Rc,))

            def LDRH_func():
                # TODO does memory read up?
                if (self.register[Rb]) % 2 != 0:
                    raise iarm.exceptions.HardFault(
                        "Memory access not half word aligned; Register: {}  Immediate: {}".format(self.register[Rb],
                                                                                                  self.convert_to_integer(
                                                                                                      Rc[1:])))
                self.register[Ra] = 0
                for i in range(2):
                    self.register[Ra] |= (self.memory[self.register[Rb] + self.convert_to_integer(Rc[1:]) + i] << (8 * i))
        else:
            self.check_arguments(low_registers=(Ra, Rb, Rc))

            def LDRH_func():
                # TODO does memory read up?
                if (self.register[Rb] + self.register[Rc]) % 2 != 0:
                    raise iarm.exceptions.HardFault(
                        "Memory access not half word aligned; Register: {}  Immediate: {}".format(self.register[Rb],
                                                                                                  self.register[Rc]))
                self.register[Ra] = 0
                for i in range(2):
                    self.register[Ra] |= (self.memory[self.register[Rb] + self.register[Rc] + i] << (8 * i))

        return LDRH_func
1125757
def -( right )
      raise "operators only on registers, not #{right.class}" unless right.is_a? RegisterValue
      op = Risc.op("#{self.type} - #{right.type}", :- , self , right )
      builder.add_code(op) if builder
      op
    end
1063263
function renderSimpleRuby( $ruby ) {
  var frag = $.create( '!' )
  var clazz = $ruby.classList
  var $rb, $ru

  frag.appendChild( $.clone( $ruby ))

  $
  .tag( 'rt', frag.firstChild )
  .forEach(function( $rt ) {
    var $rb = $.create( '!' )
    var airb = []
    var irb

    // Consider the previous nodes the implied
    // ruby base
    do {
      irb = ( irb || $rt ).previousSibling
      if ( !irb || irb.nodeName.match( /((?:h\-)?r[ubt])/i ))  break

      $rb.insertBefore( $.clone( irb ), $rb.firstChild )
      airb.push( irb )
    } while ( !irb.nodeName.match( /((?:h\-)?r[ubt])/i ))

    // Create a real `<h-ru>` to append.
    $ru = clazz.contains( 'zhuyin' ) ? createZhuyinRu( $rb, $rt ) : createNormalRu( $rb, $rt )

    // Replace the ruby text with the new `<h-ru>`,
    // and remove the original implied ruby base(s)
    try {
      $rt.parentNode.replaceChild( $ru, $rt )
      airb.map( $.remove )
    } catch ( e ) {}
  })
  return createCustomRuby( frag )
}
471033
def instruction_ROL_memory(self, opcode, ea, m):
        
        r = self.ROL(m)
#        log.debug("$%x ROL memory value $%x << 1 | Carry = $%x and write it to $%x \t| %s" % (
#            self.program_counter,
#            m, r, ea,
#            self.cfg.mem_info.get_shortest(ea)
#        ))
        return ea, r & 0xff
649832
def REV(self, params):
        
        Ra, Rb = self.get_two_parameters(self.TWO_PARAMETER_COMMA_SEPARATED, params)

        self.check_arguments(low_registers=(Ra, Rb))

        def REV_func():
            self.register[Ra] = ((self.register[Rb] & 0xFF000000) >> 24) | \
                                ((self.register[Rb] & 0x00FF0000) >> 8) | \
                                ((self.register[Rb] & 0x0000FF00) << 8) | \
                                ((self.register[Rb] & 0x000000FF) << 24)

        return REV_func
482856
def shift_handling
     op = 0
     #codes that one can shift, first two probably most common.
     # l (in lsr) means logical, ie unsigned, a (in asr) is arithmetic, ie signed
     shift_codes = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100, 'ror' => 0b110, 'rrx' => 0b110}
     shift_codes.each do |short, bin|
       long = "shift_#{short}".to_sym
       if shif = @attributes[long]
         # TODO  need more tests
         if (shif.is_a?(Numeric))
           raise "0 < shift <= 32  #{shif} #{inspect}"  if (shif >= 32) or( shif < 0)
           op |=   shift(bin  , 4 )
           op |=   shift(shif , 4+3)
         else
           bin |= 0x1;
           op  |=   shift(bin  , 4 )
           op  |=   shift(shif.reg_no , 8)
         end
         break
       end
     end
     return op
   end