Reformats the contents of the given fcd-output file into a .dri file, readable
    by PHEM. The fcd-output "fcd" must be a valid file name of an fcd-output.

    The following may be a matter of changes:
    - the engine torque is not given
420759
def fcd2dri(inpFCD, outSTRM, ignored):
    
    # print >> outSTRM, "v1\n<t>,<v>,<grad>,<n>\n[s],[km/h],[%],[1/min]\n"
    print("v1\n<t>,<v>,<grad>\n[s],[km/h],[%]", file=outSTRM)
    for q in inpFCD:
        if q.vehicle:
            for v in q.vehicle:
                percSlope = math.sin(float(v.slope)) * 100.
                print("%s,%.3f,%s" % (
                    sumolib._intTime(q.time), float(v.speed) * 3.6, percSlope), file=outSTRM)
633040
public static void write(DataOutput out, OpenFileInfo elem) throws IOException {
    OpenFileInfo info = new OpenFileInfo(elem.filePath, elem.millisOpen);
    info.write(out);
  }
446774
def convert(f, output=sys.stdout):
    

    r = f.read(11)
    if r == 'compressed\n':
        png(output, *decompress(f))
    else:
        png(output, *glue(f, r))
884477
def process_raw_data(self, fname, max_size):
        
        logging.info(f'Processing data from {fname}')
        data = []
        with open(fname) as dfile:
            for idx, line in enumerate(dfile):
                if max_size and idx == max_size:
                    break
                data.append(line)
        return data
811597
def parse_file(fname):
        
        try:
            with fopen(fname) as f:
                fstr = f.read()
        except IOError:
            if fname != 'stdin':
                raise
            sys.stdout.write('\nReading from stdin:\n\n')
            fstr = sys.stdin.read()
        fstr = fstr.replace('\r\n', '\n').replace('\r', '\n')
        if not fstr.endswith('\n'):
            fstr += '\n'
        return ast.parse(fstr, filename=fname)
267096
def SaveDataToFD(self, raw_data, fd):
    """"""
    fd.write(yaml.Dump(raw_data).encode("utf-8"))
124357
def output(self, _filename):
        

        txt = ""
        for c in self.contracts:
            (name, _inheritance, _var, func_summaries, _modif_summaries) = c.get_summary()
            txt += blue("\n+ Contract %s\n"%name)
            # (c_name, f_name, visi, _, _, _, _, _) in func_summaries
            public = [(elem[0], (elem[1], elem[2]) ) for elem in func_summaries]

            collect = collections.defaultdict(list)
            for a,b in public:
                collect[a].append(b)
            public = list(collect.items())

            for contract, functions in public:
                txt += blue("  - From {}\n".format(contract))
                functions = sorted(functions)
                for (function, visi) in functions:
                    if visi in ['external', 'public']:
                        txt += green("    - {} ({})\n".format(function, visi))
                for (function, visi) in functions:
                    if visi in ['internal', 'private']:
                        txt += magenta("    - {} ({})\n".format(function, visi))
                for (function, visi) in functions:
                    if visi not in ['external', 'public', 'internal', 'private']:
                        txt += "    - {}  ({})\n".format(function, visi)

        self.info(txt)
866301
def fhirtordf(argv: List[str], default_exit: bool = True) -> bool:
    
    dlp = dirlistproc.DirectoryListProcessor(argv,
                                             description="Convert FHIR JSON into RDF",
                                             infile_suffix=".json",
                                             outfile_suffix=".ttl",
                                             addargs=addargs,
                                             noexit=not default_exit)

    if not dlp.successful_parse:
        return False

    # Version
    if dlp.opts.version:
        print("FHIR to RDF Conversion Tool -- Version {}".format(__version__))

    # We either have to have an input file or an input directory
    if not dlp.opts.infile and not dlp.opts.indir:
        if not dlp.opts.version:
            dlp.parser.error("Either an input file or an input directory must be supplied")
        return dlp.opts.version

    # Create the output directory if needed
    if dlp.opts.outdir and not os.path.exists(dlp.opts.outdir):
        os.makedirs(dlp.opts.outdir)

    # If we are going to a single output file or stdout, gather all the input
    dlp.opts.graph = Graph() if (not dlp.opts.outfile and not dlp.opts.outdir) or\
                                (dlp.opts.outfile and len(dlp.opts.outfile) == 1) else None
    dlp.opts.fhir_metavoc = load_fhir_ontology(dlp.opts)

    # If it looks like we're processing a URL as an input file, skip the suffix check
    if dlp.opts.infile and len(dlp.opts.infile) == 1 and not dlp.opts.indir and "://" in dlp.opts.infile[0]:
        dlp.infile_suffix = ""
    dlp.outfile_suffix = '.' + suffix_for(dlp.opts.format)
    nfiles, nsuccess = dlp.run(proc=proc_file, file_filter_2=file_filter)
    if nfiles:
        if dlp.opts.graph:
            serialize_graph(dlp.opts.graph, dlp.opts.outfile[0] if dlp.opts.outfile else None, dlp.opts)
        return nsuccess > 0
    return False
614412
def output_to_firrtl(open_file, rom_blocks=None, block=None):
    
    block = working_block(block)
    f = open_file
    # write out all the implicit stuff
    f.write("circuit Example : \n")
    f.write("  module Example : \n")
    f.write("    input clock : Clock\n    input reset : UInt<1>\n")
    # write out IO signals, wires and registers
    wireRegDefs = ""
    for wire in list(block.wirevector_subset()):
        if type(wire) == Input:
            f.write("    input %s : UInt<%d>\n" % (wire.name, wire.bitwidth))
        elif type(wire) == Output:
            f.write("    output %s : UInt<%d>\n" % (wire.name, wire.bitwidth))
        elif type(wire) == WireVector:
            wireRegDefs += "    wire {} : UInt<{}>\n".format(wire.name, wire.bitwidth)
        elif type(wire) == Register:
            wireRegDefs += "    reg {} : UInt<{}>, clock\n".format(wire.name, wire.bitwidth)
        elif type(wire) == Const:
            # some const is in the form like const_0_1'b1, is this legal operation?
            wire.name = wire.name.split("'").pop(0)
            wireRegDefs += "    node {} = UInt<{}>({})\n".format(wire.name, wire.bitwidth, wire.val)
        else:
            return 1
    f.write(wireRegDefs)
    f.write("\n")

    # write "Main"
    node_cntr = 0
    initializedMem = []
    for log_net in list(block.logic_subset()):
        if log_net.op == '&':
            f.write("    %s <= and(%s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                 log_net.args[1].name))
        elif log_net.op == '|':
            f.write("    %s <= or(%s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                log_net.args[1].name))
        elif log_net.op == '^':
            f.write("    %s <= xor(%s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                 log_net.args[1].name))
        elif log_net.op == 'n':
            f.write("    node T_%d = and(%s, %s)\n" % (node_cntr, log_net.args[0].name,
                                                       log_net.args[1].name))
            f.write("    %s <= not(T_%d)\n" % (log_net.dests[0].name, node_cntr))
            node_cntr += 1
        elif log_net.op == '~':
            f.write("    %s <= not(%s)\n" % (log_net.dests[0].name, log_net.args[0].name))
        elif log_net.op == '+':
            f.write("    %s <= add(%s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                 log_net.args[1].name))
        elif log_net.op == '-':
            f.write("    %s <= sub(%s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                 log_net.args[1].name))
        elif log_net.op == '*':
            f.write("    %s <= mul(%s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                 log_net.args[1].name))
        elif log_net.op == '=':
            f.write("    %s <= eq(%s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                log_net.args[1].name))
        elif log_net.op == '<':
            f.write("    %s <= lt(%s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                log_net.args[1].name))
        elif log_net.op == '>':
            f.write("    %s <= gt(%s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                log_net.args[1].name))
        elif log_net.op == 'w':
            f.write("    %s <= %s\n" % (log_net.dests[0].name, log_net.args[0].name))
        elif log_net.op == 'x':
            f.write("    %s <= mux(%s, %s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                     log_net.args[2].name, log_net.args[1].name))
        elif log_net.op == 'c':
            f.write("    %s <= cat(%s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                 log_net.args[1].name))
        elif log_net.op == 's':
            selEnd = log_net.op_param[0]
            if len(log_net.op_param) < 2:
                selBegin = selEnd
            else:
                selBegin = log_net.op_param[len(log_net.op_param)-1]
            f.write("    %s <= bits(%s, %s, %s)\n" % (log_net.dests[0].name, log_net.args[0].name,
                                                      selBegin, selEnd))
        elif log_net.op == 'r':
            f.write("    %s <= mux(reset, UInt<%s>(0), %s)\n" %
                    (log_net.dests[0].name, log_net.dests[0].bitwidth, log_net.args[0].name))
        elif log_net.op == 'm':
            # if there are rom blocks, need to be initialized
            if rom_blocks is not None:
                if not log_net.op_param[0] in initializedMem:
                    initializedMem.append(log_net.op_param[0])

                    # find corresponding rom block according to memid
                    curr_rom = next((x for x in rom_blocks if x.id == log_net.op_param[0]), None)
                    f.write("    wire %s : UInt<%s>[%s]\n" %
                            (log_net.op_param[1].name, log_net.op_param[1].bitwidth,
                             2**log_net.op_param[1].addrwidth))

                    # if rom data is a function, calculate the data first
                    if callable(curr_rom.data):
                        romdata = [curr_rom.data(i) for i in range(2**curr_rom.addrwidth)]
                        curr_rom.data = romdata

                    # write rom block initialization data
                    for i in range(len(curr_rom.data)):
                        f.write("    %s[%s] <= UInt<%s>(%s)\n" %
                                (log_net.op_param[1].name, i, log_net.op_param[1].bitwidth,
                                 curr_rom.data[i]))

                # write the connection
                f.write("    %s <= %s[%s]\n" % (log_net.dests[0].name, log_net.op_param[1].name,
                                                log_net.args[0].name))

            else:
                if not log_net.op_param[0] in initializedMem:
                    initializedMem.append(log_net.op_param[0])
                    f.write("    cmem %s_%s : UInt<%s>[%s]\n" %
                            (log_net.op_param[1].name, log_net.op_param[0],
                             log_net.op_param[1].bitwidth, 2**log_net.op_param[1].addrwidth))
                f.write("    infer mport T_%d  = %s_%s[%s], clock\n" %
                        (node_cntr, log_net.op_param[1].name, log_net.op_param[0],
                         log_net.args[0].name))
                f.write("    %s <= T_%d\n" % (log_net.dests[0].name, node_cntr))
                node_cntr += 1
        elif log_net.op == '@':
            if not log_net.op_param[0] in initializedMem:
                initializedMem.append(log_net.op_param[0])
                f.write("    cmem %s_%s : UInt<%s>[%s]\n" %
                        (log_net.op_param[1].name, log_net.op_param[0],
                         log_net.op_param[1].bitwidth, 2**log_net.op_param[1].addrwidth))
            f.write("    when %s :\n" % log_net.args[2].name)
            f.write("      infer mport T_%d  = %s_%s[%s], clock\n" %
                    (node_cntr, log_net.op_param[1].name, log_net.op_param[0],
                     log_net.args[0].name))
            f.write("      T_%d <= %s\n" % (node_cntr, log_net.args[1].name))
            f.write("      skip\n")
            node_cntr += 1
        else:
            pass

    f.close()
    return 0
1244408
def dump(self, fname):
        
        with open(fname, 'wb') as f:
            f.write(self.output)
573370
def output(self, original_filename):
        

        for contract in self.contracts:
            for function in contract.functions + contract.modifiers:
                filename = "{}-{}-{}.dot".format(original_filename, contract.name, function.full_name)
                self.info('Export {}'.format(filename))
                function.slithir_cfg_to_dot(filename)
32372
public void dump(FormattedWriter fw)
    {
        if (TraceComponent.isAnyTracingEnabled() && tc.isEntryEnabled())
            SibTr.entry(this, tc, "dump");

        try
        {
            xmlRequestWriteOnFile(fw);
        } catch (IOException e)
        {
            // No FFDC Code Needed
            if (TraceComponent.isAnyTracingEnabled() && tc.isEventEnabled())
                SibTr.event(this, tc, "Exception caught writing Mmessage store dump!", e);
        }

        if (TraceComponent.isAnyTracingEnabled() && tc.isEntryEnabled())
            SibTr.exit(this, tc, "dump");
    }
625204
def temp_output_file(prefix="tmp", suffix="", dir=None, make_parents=False, always_clean=False):
  
  return _temp_output(False, prefix=prefix, suffix=suffix, dir=dir, make_parents=make_parents,
                      always_clean=always_clean)
870902
private File baseDir() throws IOException {
        if (baseDir == null) {
            baseDir = File.createTempFile("fcrepo-dto", null);
            if (!baseDir.delete()) {
                throw new IOException("Can't delete temp file " + baseDir);
            }
            if (!baseDir.mkdir()) {
                throw new IOException("Can't create temp dir " + baseDir);
            }
        }
        return baseDir;
    }
209339
def write_ioc_to_file(self, output_dir=None, force=False):
        
        return write_ioc(self.root, output_dir, force=force)
933948
def write_yara(self, output_file):
        
        fout = open(output_file, 'wb')
        fout.write('\n')

        for iocid in self.yara_signatures:
            signature = self.yara_signatures[iocid]
            fout.write(signature)
            fout.write('\n')

        fout.close()
        return True
576378
def write_output_files(self):
        
        os.mkdir("analysis")
        os.chdir("analysis")
        os.mkdir("hydrogen_bonds")
        os.chdir("hydrogen_bonds")
        for traj in range(len(self.trajectory)):
            with open('hbonds_data_total_'+str(traj)+'.csv', 'wb') as outfile:
                hwriter = csv.writer(outfile, delimiter=' ')
                for time in self.hbonds_by_time[traj]:
                    hwriter.writerow([time[0],time[1]])
            for bond in self.hbonds_by_type[traj]:
                if bond["donor_resnm"]=="LIG" and (bond["acceptor_idx"],bond["donor_idx"]) in [(k[0],k[3]) for k,v in self.hbonds_for_drawing.items()]:
                    with open('hbond_'+bond["acceptor_resnm"]+"_"+str(bond["acceptor_resid"])+"_"+bond["donor_atom"]+"_"+str(traj)+".csv","wb") as outfile:
                        hwriter = csv.writer(outfile, delimiter=' ')
                        for time in self.hbonds_timesteps[traj]:
                            result = [1 if x[0]==time and x["acceptor_idx"]==bond["acceptor_idx"] else 0 for x in self.hbonds[traj]][0]
                            hwriter.writerow([time,result])
                if bond["donor_resnm"]!="LIG" and (bond["donor_idx"],bond["acceptor_idx"]) in [(k[0],k[3]) for k,v in self.hbonds_for_drawing.items()]:
                    with open('hbond_'+bond["donor_resnm"]+"_"+str(bond["donor_resid"])+"_"+bond["acceptor_atom"]+"_"+str(traj)+".csv","wb") as outfile:
                        hwriter = csv.writer(outfile, delimiter=' ')
                        for time in self.hbonds_timesteps[traj]:
                            result = [1 if x[0]==time and x["donor_idx"]==bond["donor_idx"] else 0 for x in self.hbonds[traj]][0]
                            hwriter.writerow([time,result])
        os.chdir("../../")