_control;
	priv_ops->do_getnf = ar9003_hw_do_getnf;
	priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
	priv_ops->set_radar_params = ar9003_hw_set_radar_params;
	priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;

	ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
	ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
	ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
	ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
	ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;

#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
	ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
#endif
	ops->tx99_start = ar9003_hw_tx99_start;
	ops->tx99_stop = ar9003_hw_tx99_stop;
	ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;

	ar9003_hw_set_nf_limits(ah);
	ar9003_hw_set_radar_conf(ah);
	memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
}

/*
 * Baseband Watchdog signatures:
 *
 * 0x04000539: BB hang when operating in HT40 DFS Channel.
 *             Full chip reset is not required, but a recovery
 *             mechanism is needed.
 *
 * 0x1300000a: Related to CAC deafness.
 *             Chip reset is not required.
 *
 * 0x0400000a: Related to CAC deafness.
 *             Full chip reset is required.
 *
 * 0x04000b09: RX state machine gets into an illegal state
 *             when a packet with unsupported rate is received.
 *             Full chip reset is required and PHY_RESTART has
 *             to be disabled.
 *
 * 0x04000409: Packet stuck on receive.
 *             Full chip reset is required for all chips except
 *	       AR9340, AR9531 and AR9561.
 */

/*
 * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
 */
bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
{
	u32 val;

	switch(ah->bb_watchdog_last_status) {
	case 0x04000539:
		val = REG_READ(ah, AR_PHY_RADAR_0);
		val &= (~AR_PHY_RADAR_0_FIRPWR);
		val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
		REG_WRITE(ah, AR_PHY_RADAR_0, val);
		udelay(1);
		val = REG_READ(ah, AR_PHY_RADAR_0);
		va