b_conf_set(struct ath_hw *ah,
				   struct ath_hw_antcomb_conf *antconf)
{
	u32 regval;

	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
	regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
		    AR_PHY_ANT_DIV_ALT_LNACONF |
		    AR_PHY_ANT_FAST_DIV_BIAS |
		    AR_PHY_ANT_DIV_MAIN_GAINTB |
		    AR_PHY_ANT_DIV_ALT_GAINTB);
	regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
		   & AR_PHY_ANT_DIV_MAIN_LNACONF);
	regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
		   & AR_PHY_ANT_DIV_ALT_LNACONF);
	regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
		   & AR_PHY_ANT_FAST_DIV_BIAS);
	regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
		   & AR_PHY_ANT_DIV_MAIN_GAINTB);
	regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
		   & AR_PHY_ANT_DIV_ALT_GAINTB);

	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
}

#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT

static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
{
	struct ath9k_hw_capabilities *pCap = &ah->caps;
	u8 ant_div_ctl1;
	u32 regval;

	if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
		return;

	if (AR_SREV_9485(ah)) {
		regval = ar9003_hw_ant_ctrl_common_2_get(ah,
						 IS_CHAN_2GHZ(ah->curchan));
		if (enable) {
			regval &= ~AR_SWITCH_TABLE_COM2_ALL;
			regval |= ah->config.ant_ctrl_comm2g_switch_enable;
		}
		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
			      AR_SWITCH_TABLE_COM2_ALL, regval);
	}

	ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);

	/*
	 * Set MAIN/ALT LNA conf.
	 * Set MAIN/ALT gain_tb.
	 */
	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
	regval &= (~AR_ANT_DIV_CTRL_ALL);
	regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

	if (AR_SREV_9485_11_OR_LATER(ah)) {
		/*
		 * Enable LNA diversity.
		 */
		regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
		regval &= ~AR_PHY_ANT_DIV_LNADIV;
		regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
		if (enable)
			regval |= AR_ANT_DIV_ENABLE;

		REG_WRITE(ah, AR_PHY_MC