      srd_bit_index++;
        }
    }
    
    return(srd_bits);
}



/**************************************************************************/ 
/*                                                                        */ 
/*  FUNCTION                                               RELEASE        */ 
/*                                                                        */ 
/*    _txm_module_manager_mm_register_setup          Cortex-M7/MPU/IAR    */ 
/*                                                           6.0.1        */
/*  AUTHOR                                                                */
/*                                                                        */
/*    Scott Larson, Microsoft Corporation                                 */
/*                                                                        */
/*  DESCRIPTION                                                           */ 
/*                                                                        */ 
/*    This function sets up the MPU register definitions based on the     */ 
/*    module's memory characteristics.                                    */ 
/*    MPU layout for the Cortex-M7:                                       */ 
/*    Entry     Description                                               */ 
/*      0       Kernel mode entry                                         */ 
/*      1       Module code region                                        */ 
/*      2       Module code region                                        */ 
/*      3       Module code region                                        */ 
/*      4       Module code region                                        */ 
/*      5       Module data region                                        */ 
/*      6       Module data region                                        */ 
/*      7       Module data region                                        */ 
/*      8       Module data region                                        */ 
/*      9       Module shared me