 EBI_DEV1_ACK_RM_CNT_OFFS)
#define EBI_DEV2_DMA_EXT_ADDR_OFFS	0x00000200
#define EBI_DEV2_DMA_EXT_ADDR(base)	((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
#define EBI_DEV2_EXT_ACC_OFFS		0x00000204
#define EBI_DEV2_EXT_ACC(base)		((base) + EBI_DEV2_EXT_ACC_OFFS)
#define EBI_DEV2_CONFIG1_OFFS		0x00000208
#define EBI_DEV2_CONFIG1(base)		((base) + EBI_DEV2_CONFIG1_OFFS)
#define EBI_DEV2_CONFIG2_OFFS		0x0000020C
#define EBI_DEV2_CONFIG2(base)		((base) + EBI_DEV2_CONFIG2_OFFS)
#define EBI_DEV2_FIFO_CONFIG_OFFS	0x00000210
#define EBI_DEV2_FIFO_CONFIG(base)	((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
#define EBI_DEV2_FLASH_CONF_ST_OFFS	0x00000214
#define EBI_DEV2_FLASH_CONF_ST(base)	((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
#define EBI_DEV2_DMA_CONFIG1_OFFS	0x00000218
#define EBI_DEV2_DMA_CONFIG1(base)	((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
#define EBI_DEV2_DMA_CONFIG2_OFFS	0x0000021C
#define EBI_DEV2_DMA_CONFIG2(base)	((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
#define EBI_DEV2_DMA_ECC_CTRL_OFFS	0x00000220
#define EBI_DEV2_DMA_ECC_CTRL(base)	((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
#define EBI_DEV2_TIM1_RD1_OFFS		0x00000224
#define EBI_DEV2_TIM1_RD1(base)		((base) + EBI_DEV2_TIM1_RD1_OFFS)
#define EBI_DEV2_TIM1_RD2_OFFS		0x00000228
#define EBI_DEV2_TIM1_RD2(base)		((base) + EBI_DEV2_TIM1_RD2_OFFS)
#define EBI_DEV2_TIM1_WR1_OFFS		0x0000022C
#define EBI_DEV2_TIM1_WR1(base)		((base) + EBI_DEV2_TIM1_WR1_OFFS)
#define EBI_DEV2_TIM1_WR2_OFFS		0x00000230
#define EBI_DEV2_TIM1_WR2(base)		((base) + EBI_DEV2_TIM1_WR2_OFFS)
#define EBI_DEV2_TIM_EXT_OFFS		0x00000234
#define EBI_DEV2_TIM_EXT(base)		((base) + EBI_DEV2_TIM_EXT_OFFS)
#define EBI_DEV2_TIM2_CFI_RD1_OFFS	0x00000238
#define EBI_DEV2_TIM2_CFI_RD1(base)	((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
#define EBI_DEV2_TIM2_CFI_RD2_OFFS	0x0000023C
#define EBI_DEV2_TIM2_CFI_RD2(base)	((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
#define EBI_DEV2_TIM3_DMA1_OFFS		0x00000240
#define EBI_DEV2_TIM3_DMA1(base)	((base) + EBI_DEV2_TIM3_DMA1_OFFS)
#define EBI_DEV2_TIM3_DMA2_OFFS		0x00000244
#define EBI_DEV2_TIM3_DMA2(base)	((base) + 