) & AT91_SSC_FSOS)
			| (((bits - 1)			<< 16) & AT91_SSC_FSLEN)
			| (((channels - 1)		<<  8) & AT91_SSC_DATNB)
			| (( 1				<<  7) & AT91_SSC_MSBF)
			| (( 0				<<  5) & AT91_SSC_LOOP)
			| (((bits - 1)			<<  0) & AT91_SSC_DATALEN);

		tcmr =	  (( ssc_p->tcmr_period		<< 24) & AT91_SSC_PERIOD)
			| (( 1				<< 16) & AT91_SSC_STTDLY)
			| (( AT91_SSC_START_FALLING_RF       ) & AT91_SSC_START)
			| (( AT91_SSC_CKI_FALLING	     ) & AT91_SSC_CKI)
			| (( AT91_SSC_CKO_CONTINUOUS	     ) & AT91_SSC_CKO)
			| (( AT91_SSC_CKS_DIV		     ) & AT91_SSC_CKS);

		tfmr =	  (( AT91_SSC_FSEDGE_POSITIVE	     ) & AT91_SSC_FSEDGE)
			| (( 0				<< 23) & AT91_SSC_FSDEN)
			| (( AT91_SSC_FSOS_NEGATIVE	     ) & AT91_SSC_FSOS)
			| (((bits - 1)			<< 16) & AT91_SSC_FSLEN)
			| (((channels - 1)		<<  8) & AT91_SSC_DATNB)
			| (( 1				<<  7) & AT91_SSC_MSBF)
			| (( 0				<<  5) & AT91_SSC_DATDEF)
			| (((bits - 1)			<<  0) & AT91_SSC_DATALEN);
		break;

	case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
		/*
		 * I2S format, CODEC supplies BCLK and LRC clocks.
		 *
		 * The SSC transmit clock is obtained from the BCLK signal on
		 * on the TK line, and the SSC receive clock is generated from the
		 * transmit clock.
		 *
		 * For single channel data, one sample is transferred on the falling
		 * edge of the LRC clock.  For two channel data, one sample is
		 * transferred on both edges of the LRC clock.
		 */
		start_event = channels == 1
				? AT91_SSC_START_FALLING_RF
				: AT91_SSC_START_EDGE_RF;

		rcmr =	  (( 0				<< 24) & AT91_SSC_PERIOD)
			| (( 1				<< 16) & AT91_SSC_STTDLY)
			| (( start_event		     ) & AT91_SSC_START)
			| (( AT91_SSC_CK_RISING		     ) & AT91_SSC_CKI)
			| (( AT91_SSC_CKO_NONE		     ) & AT91_SSC_CKO)
			| (( AT91_SSC_CKS_CLOCK		     ) & AT91_SSC_CKS);

		rfmr =	  (( AT91_SSC_FSEDGE_POSITIVE	     ) & AT91_SSC_FSEDGE)
			| (( AT91_SSC_FSOS_NONE		     ) & AT91_SSC_FSOS)
			| (( 0				<< 16) & AT91_SSC_FSLEN)
			| (( 0				<<  8) & AT91_SSC_DATNB)
			| (( 1				<<  7) & AT91_SSC_MSBF)
			| (( 0				<<  5) & AT91_SSC_LOOP)
			