I_DEV1_CONFIG1_OFFS)
#define EBI_DEV1_CONFIG2_OFFS		0x0000010C
#define EBI_DEV1_CONFIG2(base)		((base) + EBI_DEV1_CONFIG2_OFFS)
#define EBI_DEV1_FIFO_CONFIG_OFFS	0x00000110
#define EBI_DEV1_FIFO_CONFIG(base)	((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
#define EBI_DEV1_FLASH_CONF_ST_OFFS	0x00000114
#define EBI_DEV1_FLASH_CONF_ST(base)	((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
#define EBI_DEV1_DMA_CONFIG1_OFFS	0x00000118
#define EBI_DEV1_DMA_CONFIG1(base)	((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
#define EBI_DEV1_DMA_CONFIG2_OFFS	0x0000011C
#define EBI_DEV1_DMA_CONFIG2(base)	((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
#define EBI_DEV1_DMA_ECC_CTRL_OFFS	0x00000120
#define EBI_DEV1_DMA_ECC_CTRL(base)	((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
#define EBI_DEV1_TIM1_RD1_OFFS		0x00000124
#define EBI_DEV1_TIM1_RD1(base)		((base) + EBI_DEV1_TIM1_RD1_OFFS)
#define EBI_DEV1_TIM1_RD2_OFFS		0x00000128
#define EBI_DEV1_TIM1_RD2(base)		((base) + EBI_DEV1_TIM1_RD2_OFFS)
#define EBI_DEV1_TIM1_WR1_OFFS		0x0000012C
#define EBI_DEV1_TIM1_WR1(base)		((base) + EBI_DEV1_TIM1_WR1_OFFS)
#define EBI_DEV1_TIM1_WR2_OFFS		0x00000130
#define EBI_DEV1_TIM1_WR2(base)		((base) + EBI_DEV1_TIM1_WR2_OFFS)
#define EBI_DEV1_TIM_EXT_OFFS		0x00000134
#define EBI_DEV1_TIM_EXT(base)		((base) + EBI_DEV1_TIM_EXT_OFFS)
#define EBI_DEV1_TIM2_CFI_RD1_OFFS	0x00000138
#define EBI_DEV1_TIM2_CFI_RD1(base)	((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
#define EBI_DEV1_TIM2_CFI_RD2_OFFS	0x0000013C
#define EBI_DEV1_TIM2_CFI_RD2(base)	((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
#define EBI_DEV1_TIM3_DMA1_OFFS		0x00000140
#define EBI_DEV1_TIM3_DMA1(base)	((base) + EBI_DEV1_TIM3_DMA1_OFFS)
#define EBI_DEV1_TIM3_DMA2_OFFS		0x00000144
#define EBI_DEV1_TIM3_DMA2(base)	((base) + EBI_DEV1_TIM3_DMA2_OFFS)
#define EBI_DEV1_TIM4_UDMA1_OFFS	0x00000148
#define EBI_DEV1_TIM4_UDMA1(base)	((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
#define EBI_DEV1_TIM4_UDMA2_OFFS	0x0000014C
#define EBI_DEV1_TIM4_UDMA2(base)	((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
#define EBI_DEV1_ACK_RM_CNT_OFFS	0x00000150
#define EBI_DEV1_ACK_RM_CNT(base)	((base) +