 for performing signed multiplication. The Baugh-Wooley algorithm implementation typically utilizes a linear summation array that results in fewer components and less complexity than multipliers using the Booth encoding algorithm. However, such prior art multipliers implementing a linear summation array utilizing the Baugh-Wooley algorithm only allow for signed multiplication to be performed. Accordingly, such multiplier implementations are severely limited in that they are unable to perform unsigned multiplication.
In view of the above, a desire exists for a high-speed multiplier that includes a linear summation array for performing both signed and unsigned multiplication. A further desire exists for a multiplier having a static design. Still a further desire exists for a multiplier that reduces the amount of circuitry and routing complexity of prior art multipliers.
These and other objects, features and technical advantages are achieved by a system and method which provide a multiplier comprising a linear summation array that is implemented in a manner that enables both signed and unsigned multiplication to be performed. A preferred embodiment utilizes a modified Baugh-Wooley algorithm to enable an optimum even-and-odd linear summation array for performing both signed and unsigned high speed multiplication. That is, a preferred embodiment enables a linear summation array that is smaller in size and simpler in design than the multiplier arrays typically implemented for signed multiplication in the prior art. For example, suppose 16-bit by 16-bit multiplication is being performed, a preferred embodiment utilizes a linear summation array that is 16 by 14, rather than the prior art multiplier arrays that are typically 22 by 14 because of the additional sign extension columns utilized in prior art designs.
Therefore, the resulting columns of the multiplier array of a preferred embodiment exactly fit into the input pitch of the operands, which dramatically reduces the number of circuitry components required to be imp