tream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct at91_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
	struct at91_pcm_dma_params *dma_params;
	int dir;

	dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
	dma_params = ssc_p->dma_params[dir];

	at91_ssc_write(dma_params->ssc_base + AT91_SSC_CR,
			dma_params->mask->ssc_enable);

	DBG("%s enabled SSC_SR=0x%08lx\n", dir ? "receive" : "transmit",
		at91_ssc_read(dma_params->ssc_base + AT91_SSC_SR));
	return 0;
}


#ifdef CONFIG_PM
static int at91_ssc_suspend(struct platform_device *pdev,
	struct snd_soc_cpu_dai *cpu_dai)
{
	struct at91_ssc_info *ssc_p;

	if(!cpu_dai->active)
		return 0;

	ssc_p = &ssc_info[cpu_dai->id];

	/* Save the status register before disabling transmit and receive. */
	ssc_p->ssc_state.ssc_sr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR);
	at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR,
			AT91_SSC_TXDIS | AT91_SSC_RXDIS);

	/* Save the current interrupt mask, then disable unmasked interrupts. */
	ssc_p->ssc_state.ssc_imr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_IMR);
	at91_ssc_write(ssc_p->ssc.base + AT91_SSC_IDR, ssc_p->ssc_state.ssc_imr);

	ssc_p->ssc_state.ssc_cmr  = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_CMR);
	ssc_p->ssc_state.ssc_rcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR);
	ssc_p->ssc_state.ssc_rfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RFMR);
	ssc_p->ssc_state.ssc_tcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_TCMR);
	ssc_p->ssc_state.ssc_tfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_TFMR);

	return 0;
}

static int at91_ssc_resume(struct platform_device *pdev,
	struct snd_soc_cpu_dai *cpu_dai)
{
	struct at91_ssc_info *ssc_p;

	if(!cpu_dai->active)
		return 0;

	ssc_p = &ssc_info[cpu_dai->id];

	at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TFMR, ssc_p->ssc_state.ssc_tfmr);
	at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TCMR, ssc_p->ssc_state.ssc_tcmr);
	at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RFMR, ssc_p->ssc_state.ssc_rfmr);
	at91_ssc_write(ssc_p->ssc.base + AT91_