  ) & AT91_SSC_FSOS)
			| (( 0				<< 16) & AT91_SSC_FSLEN)
			| (((channels - 1)		<<  8) & AT91_SSC_DATNB)
			| (( 1				<<  7) & AT91_SSC_MSBF)
			| (( 0				<<  5) & AT91_SSC_DATDEF)
			| (((bits - 1)			<<  0) & AT91_SSC_DATALEN);



			break;

	case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
	default:
		printk(KERN_WARNING "at91-ssc: unsupported DAI format 0x%x.\n",
			ssc_p->daifmt);
		return -EINVAL;
		break;
	}
	DBG("RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", rcmr, rfmr, tcmr, tfmr);

	if (!ssc_p->initialized) {

		/* Enable PMC peripheral clock for this SSC */
		DBG("Starting pid %d clock\n", ssc_p->ssc.pid);
		at91_sys_write(AT91_PMC_PCER, 1<<ssc_p->ssc.pid);

		/* Reset the SSC and its PDC registers */
		at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, AT91_SSC_SWRST);

		at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RPR, 0);
		at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RCR, 0);
		at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RNPR, 0);
		at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RNCR, 0);
		at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TPR, 0);
		at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TCR, 0);
		at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TNPR, 0);
		at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TNCR, 0);

		if ((ret = request_irq(ssc_p->ssc.pid, at91_ssc_interrupt,
					0, ssc_p->name, ssc_p)) < 0) {
			printk(KERN_WARNING "at91-ssc: request_irq failure\n");

			DBG("Stopping pid %d clock\n", ssc_p->ssc.pid);
			at91_sys_write(AT91_PMC_PCER, 1<<ssc_p->ssc.pid);
			return ret;
		}

		ssc_p->initialized = 1;
	}

	/* set SSC clock mode register */
	at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CMR, ssc_p->cmr_div);

	/* set receive clock mode and format */
	at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, rcmr);
	at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RFMR, rfmr);

	/* set transmit clock mode and format */
	at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TCMR, tcmr);
	at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TFMR, tfmr);

	DBG("hw_params: SSC initialized\n");
	return 0;
}


static int at91_ssc_prepare(struct snd_pcm_subs