_GAIN_CTRL, regval);

		/*
		 * Enable fast antenna diversity.
		 */
		regval = REG_READ(ah, AR_PHY_CCK_DETECT);
		regval &= ~AR_FAST_DIV_ENABLE;
		regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
		if (enable)
			regval |= AR_FAST_DIV_ENABLE;

		REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);

		if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
			regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
			regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
				     AR_PHY_ANT_DIV_ALT_LNACONF |
				     AR_PHY_ANT_DIV_ALT_GAINTB |
				     AR_PHY_ANT_DIV_MAIN_GAINTB));
			/*
			 * Set MAIN to LNA1 and ALT to LNA2 at the
			 * beginning.
			 */
			regval |= (ATH_ANT_DIV_COMB_LNA1 <<
				   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
			regval |= (ATH_ANT_DIV_COMB_LNA2 <<
				   AR_PHY_ANT_DIV_ALT_LNACONF_S);
			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
		}
	} else if (AR_SREV_9565(ah)) {
		if (enable) {
			REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
				    AR_ANT_DIV_ENABLE);
			REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
				    (1 << AR_PHY_ANT_SW_RX_PROT_S));
			REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
				    AR_FAST_DIV_ENABLE);
			REG_SET_BIT(ah, AR_PHY_RESTART,
				    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
			REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
				    AR_BTCOEX_WL_LNADIV_FORCE_ON);
		} else {
			REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
				    AR_ANT_DIV_ENABLE);
			REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
				    (1 << AR_PHY_ANT_SW_RX_PROT_S));
			REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
				    AR_FAST_DIV_ENABLE);
			REG_CLR_BIT(ah, AR_PHY_RESTART,
				    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
			REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
				    AR_BTCOEX_WL_LNADIV_FORCE_ON);

			regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
			regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
				    AR_PHY_ANT_DIV_ALT_LNACONF |
				    AR_PHY_ANT_DIV_MAIN_GAINTB |
				    AR_PHY_ANT_DIV_ALT_GAINTB);
			regval |= (ATH_ANT_DIV_COMB_LNA1 <<
				   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
			regval |= (ATH_ANT_DIV_COMB_LNA2 <<
				   AR_PHY_ANT_DIV_ALT_LNACONF_S);
			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg