EBI_DEV2_TIM3_DMA2_OFFS)
#define EBI_DEV2_TIM4_UDMA1_OFFS	0x00000248
#define EBI_DEV2_TIM4_UDMA1(base)	((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
#define EBI_DEV2_TIM4_UDMA2_OFFS	0x0000024C
#define EBI_DEV2_TIM4_UDMA2(base)	((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
#define EBI_DEV2_ACK_RM_CNT_OFFS	0x00000250
#define EBI_DEV2_ACK_RM_CNT(base)	((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
#define EBI_DEV3_DMA_EXT_ADDR_OFFS	0x00000300
#define EBI_DEV3_DMA_EXT_ADDR(base)	((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
#define EBI_DEV3_EXT_ACC_OFFS		0x00000304
#define EBI_DEV3_EXT_ACC(base)		((base) + EBI_DEV3_EXT_ACC_OFFS)
#define EBI_DEV3_CONFIG1_OFFS		0x00000308
#define EBI_DEV3_CONFIG1(base)		((base) + EBI_DEV3_CONFIG1_OFFS)
#define EBI_DEV3_CONFIG2_OFFS		0x0000030C
#define EBI_DEV3_CONFIG2(base)		((base) + EBI_DEV3_CONFIG2_OFFS)
#define EBI_DEV3_FIFO_CONFIG_OFFS	0x00000310
#define EBI_DEV3_FIFO_CONFIG(base)	((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
#define EBI_DEV3_FLASH_CONF_ST_OFFS	0x00000314
#define EBI_DEV3_FLASH_CONF_ST(base)	((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
#define EBI_DEV3_DMA_CONFIG1_OFFS	0x00000318
#define EBI_DEV3_DMA_CONFIG1(base)	((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
#define EBI_DEV3_DMA_CONFIG2_OFFS	0x0000031C
#define EBI_DEV3_DMA_CONFIG2(base)	((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
#define EBI_DEV3_DMA_ECC_CTRL_OFFS	0x00000320
#define EBI_DEV3_DMA_ECC_CTRL(base)	((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
#define EBI_DEV3_TIM1_RD1_OFFS		0x00000324
#define EBI_DEV3_TIM1_RD1(base)		((base) + EBI_DEV3_TIM1_RD1_OFFS)
#define EBI_DEV3_TIM1_RD2_OFFS		0x00000328
#define EBI_DEV3_TIM1_RD2(base)		((base) + EBI_DEV3_TIM1_RD2_OFFS)
#define EBI_DEV3_TIM1_WR1_OFFS		0x0000032C
#define EBI_DEV3_TIM1_WR1(base)		((base) + EBI_DEV3_TIM1_WR1_OFFS)
#define EBI_DEV3_TIM1_WR2_OFFS		0x00000330
#define EBI_DEV3_TIM1_WR2(base)		((base) + EBI_DEV3_TIM1_WR2_OFFS)
#define EBI_DEV3_TIM_EXT_OFFS		0x00000334
#define EBI_DEV3_TIM_EXT(base)		((base) + EBI_DEV3_TIM_EXT_OFFS)
#define EBI_DEV3_TIM2_CFI_RD1_OFFS	0x00000338
#define EBI_DEV3_TIM2_CFI_RD1(base)	((base) + EBI_DEV