};
	unsigned int i;

	txpower = txpower <= MAX_RATE_POWER ? txpower : MAX_RATE_POWER;
	for (i = 0; i < ar9300RateSize; i++)
		p_pwr_array[i] = txpower;

	ar9003_hw_tx_power_regwrite(ah, p_pwr_array);
}

static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array)
{
	ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L];
	ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L];
	ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L],
			      rate_array[ALL_TARGET_LEGACY_5S]);
	ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L],
			      rate_array[ALL_TARGET_LEGACY_11S]);
}

static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array,
					int offset)
{
	int i, j;

	for (i = offset; i < offset + AR9300_OFDM_RATES; i++) {
		/* OFDM rate to power table idx */
		j = ofdm2pwr[i - offset];
		ah->tx_power[i] = rate_array[j];
	}
}

static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array,
				      int ss_offset, int ds_offset,
				      int ts_offset, bool is_40)
{
	int i, j, mcs_idx = 0;
	const u8 *mcs2pwr = (is_40) ? mcs2pwr_ht40 : mcs2pwr_ht20;

	for (i = ss_offset; i < ss_offset + AR9300_HT_SS_RATES; i++) {
		j = mcs2pwr[mcs_idx];
		ah->tx_power[i] = rate_array[j];
		mcs_idx++;
	}

	for (i = ds_offset; i < ds_offset + AR9300_HT_DS_RATES; i++) {
		j = mcs2pwr[mcs_idx];
		ah->tx_power[i] = rate_array[j];
		mcs_idx++;
	}

	for (i = ts_offset; i < ts_offset + AR9300_HT_TS_RATES; i++) {
		j = mcs2pwr[mcs_idx];
		ah->tx_power[i] = rate_array[j];
		mcs_idx++;
	}
}

static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset,
					int ds_offset, int ts_offset)
{
	memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset],
	       AR9300_HT_SS_RATES);
	memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset],
	       AR9300_HT_DS_RATES);
	memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset],
	       AR9300_HT_TS_RATES);
}

void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
				 struct ath9k_channel *chan)
{
	if (IS_CHAN_5GHZ(ch